Integrated graphics subsystem with message-passing architecture

Details Integrated graphics subsystem with message-passing architecture Integrated graphics subsystem with message-passing architecture

1998-12-09

2000-11-28

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345505, 345519, 345521, G06T 120

Patent

active

061542237

ABSTRACT:
A graphics processing chip which uses a deep pipeline of multiple asynchronous units to achieve a high net throughput in 3D rendering. Preferably reads and writes to a local buffer are provided by separate stages of the pipeline. Preferably some of the individual units include parallel paths internally. Preferably some of the individual units are connected to look ahead by more than one stage, to keep the pipeline filled while minimizing the use of expensive deep FIFOs.

REFERENCES:
patent: 4866637 (1989-09-01), Gonzalez-Lopez et al.
patent: 5440682 (1995-08-01), Deering
patent: 5798700 (1998-08-01), Baldwin
patent: 6025853 (2000-02-01), Baldwin

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