Integrated FET circuit with input current cancellation

Details Integrated FET circuit with input current cancellation Integrated FET circuit with input current cancellation

1976-12-13

1978-01-10

Miller, Jr., Stanley D.

Amplifiers

Signal feedback

Combined with control of bias voltage of signal amplifier

357 22, 357 36, 330307, 330227, 330288, 307299B, 307304, H01L 2702

Patent

active

040682544

ABSTRACT:
An integrated circuit including an FET and an analog for cancelling input current that would otherwise be required to supply the FET gate leakage current. The analog establishes a leakage current the magnitude of which is a substantially fixed proportion of the FET leakage current over a given operating range, and employs proportional current mirror means referenced to the analog leakage current to supply the FET leakage current and thereby substantially cancel the input bias current. In a preferred embodiment the analog comprises a lateral PNP multi-collector transistor with one collector connected to its base to establish a reference current, another collector providing the cancellation current, and its base voltage tracking the FET gate voltage so that the two leakage currents remain substantially equal. An analog FET may also be employed to cancel gate-to-drain and gate-to-source leakages. A description of the invention as applied to an operational amplifier is given.

REFERENCES:
patent: 3278853 (1966-10-01), Lin
patent: 3558921 (1971-01-01), Yokozawa et al.
patent: 3703650 (1972-11-01), Kendall
patent: 4008441 (1977-02-01), Schade
patent: 4028564 (1977-06-01), Streit et al.
K. Beilstein et al., "Monitor ckt. for Leakage Sensitive FET Devices," IBM Tech. Discl. Bull., vol. 19, No. 3, Aug. 1976, pp. 1000-1001.

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