Electricity: power supply or regulation systems – In shunt with source or load – Using a three or more terminal semiconductive device
Reexamination Certificate
2002-02-04
2003-08-05
Riley, Shawn (Department: 2838)
Electricity: power supply or regulation systems
In shunt with source or load
Using a three or more terminal semiconductive device
C323S284000
Reexamination Certificate
active
06603291
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to an integrated FET and driver, particularly but not exclusively for use in a synchronous dc—dc conversion circuit.
Direct current (dc) to dc converters are known in the art, and are generally used to convert from one dc voltage level to another, for example to provide a 1.5V voltage rail from a 12V voltage supply.
One type of converter, a synchronous dc—dc converter, is illustrated schematically in FIG.
1
. An input voltage V
in
is applied between input terminals
2
,
4
. A pair of transistors, here field effect transistors
6
,
8
, are connected between the input terminals
2
,
4
. The transistor
6
adjacent to the input terminal
2
is known as the control FET or high side transistor, and the transistor
8
adjacent to the ground is known as the synchronous (sync) FET or low side transistor. The high side is relatively more positive than the low side, though it is not necessary that either the high or the low side has any particular relationship to ground.
The node between the transistors
6
,
8
is known as the switch node
10
. The switch node feeds through an inductor
12
and across a capacitor
14
to an output
16
.
The control and sync FETs are driven by respective drivers
30
,
32
.
A control circuit
18
has one input on an input control terminal
20
and another input fed from the output
16
via a feedback path
22
. The control circuit
18
supplies control signals to control the FETs
6
,
8
to maintain a constant voltage at the output by switching transistors
6
,
8
off and on alternately. The control signals are alternating signals which cause the control and sync FETs to conduct alternately. The mark-space ratio is varied, i.e. the ratio of the time for which the control FET conducts to the time the sync FET conducts is modulated, to achieve the desired voltage on the output
16
.
Examples of such dc—dc converters include those presented in WO98/49607 to Intel Corporation and U.S. Pat. No. 5,479,089 to Lee.
One feature of synchronous dc—dc converters is that it is not generally desired to switch on both high and low side transistors
6
,
8
simultaneously. If both transistors are on, the input voltage is short-circuited by current passing directly between the two input terminals
2
,
4
through the control and sync FETs. The phenomenon known as “shoot-through”. Accordingly, the control circuit
18
is generally arranged to ensure that only one of the two transistors
6
,
8
is on at a time.
This is conventionally carried out by monitoring two voltages. The voltage at the switch node
10
is monitored to prevent the switching on of the low side transistor
8
until the high side transistor
6
is switched off. The voltage at the gate
24
of the low side transistor
8
is monitored to prevent the high side transistor switching on until the low side transistor
8
is switched off. WO98/49607 describes a circuit of this type, as does U.S. Pat. No. 5,479,089 to Lee.
The dead time when neither FET is conducting depends on the transistor threshold voltage and the capacitance of the sync FET, which vary widely due to manufacturing spread of parameters of the chosen FET, as well as according to the individual choice of FET. This means that a control IC has to use conservative estimates of these parameters to produce a dead time that will avoid shoot through. This is generally a longer dead time than would be possible if the control circuit were optimised for the specific FETs used.
The present trend is to increase switching and clock speeds, which increases the significance of the dead time during which neither high or low side transistor
6
,
8
is on. It would be beneficial to reduce this time.
A further disadvantage occurs in the case that a plurality of FETs in parallel are used in place of the single high and low side transistors. The parallel FETs never switch at exactly the same time due to different gate resistances and other parameters caused again by manufacturing variations or variability in the circuit in which the FETs are provided. Thus, it becomes difficult to correctly determine when all of the high side or low side FETs are switched off and accordingly when the other FETs can be switched on. The solution generally adopted is to include a gate resistor in the circuit, but this slows down the switching of the MOSFETs and increases switching losses, especially at high frequencies. Accordingly, it would be beneficial to provide a circuit arrangement that could more easily use parallel FETs.
BRIEF DESCRIPTION OF THE DRAWINGS
An implementation of such a synchronous circuit is shown in
FIG. 2. A
driver IC
120
integrates in a single package
130
a timing circuit
150
, a driver
30
for an external control FET
6
and a driver
32
for an external sync FET
8
. An external control circuit
18
, not shown in
FIG. 2
, provides a PWM control signal to the timing circuit
150
. A voltage is provided between input terminals
80
,
82
on the package
130
to provide the electric power to the timing circuit
150
. One of the input terminals
82
is a ground terminal connected to ground rail
140
, to which the sync FET
8
is also connected. The control FET driver
30
is driven by the voltage between a separate voltage input
134
and the switch node
10
between the control
6
and sync
8
FETs. The control FET driver
30
operates at different dc voltage from the sync FET driver
32
, and so is isolated from the sync FET driver
32
and the control circuit
150
. Further, a level shift circuit
132
allows signal to pass from the timing circuit
150
to the control FET driver
30
whilst keeping the control FET driver
30
isolated. The control FET driver
30
is thus able to “float” with respect to circuit ground.
A problem with this circuit is that it suffers from switching frequency limitations, due at least in part to the effects of the parasitic inductance in various lead wires which can lead to disturbances in the gate or ground voltage depending on the exact connection arrangement used.
SUMMARY OF THE INVENTION
According to the invention there is provided a low side component comprising a sync FET having a source, a drain and a gate; a driver circuit powered between high and low voltage power connections and with an output connected to the gate of the sync FET for driving the sync FET; a timing circuit for controlling the driver circuit in accordance with a signal on a control input; wherein the driver circuit is isolated from the timing circuit and the low voltage power connection of the driver circuit is directly connected to the source of the sync FET.
Thus, the invention provides a low side FET switch device wherein the FET has an internal direct connection between the source electrode of the FET and the low side of its related gate driver circuit.
This local connection may in particular be a low inductance connection.
Alternative ways of connecting the low side driver suffer from various disadvantages.
One option might be simply to connect the low side driver ground to the circuit ground. This solution is essentially that used in present day circuit arrangements using discrete components (e.g. FIG.
2
). However, this approach results in two problems. Firstly, the area enclosed by the circuit loop connecting the driver to the MOSFET gate on one hand and through the ground to the MOSFET source on the other, is relatively large. This results in a high inductance in the gate drive circuit which limits the response time of the gate-source voltage and hence limits the switching speed. Secondly, the high rate of change of current when the FET is switched generates a voltage across the parasitic inductance in the source connection. At turn on of the FET, this reduces the gate-source voltage across the FET chip and slows the switching of the FET. At turn off of the FET, this generates a positive spike on the gate-source voltage which tends to turn the FET back on, this phenomenon being commonly known as “gate bounce”.
An alternative option might be to simply connect the driver ground
De Groot Leonardus A.
Rutter Philip
Wheeler Nicolas J.
Biren Steven R.
Riley Shawn
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