Integrated dual-slope analog to digital converter with R/C varia

Details Integrated dual-slope analog to digital converter with R/C varia Integrated dual-slope analog to digital converter with R/C varia

1989-04-27

1990-03-20

Shoop, Jr., William M.

Coded data generation or conversion

Converter compensation

341167, H03M 106

Patent

active

049105167

ABSTRACT:
A dual-slope A/D converter circuit has an oscillator (14) whose timing frequency is determined by the value of an oscillator resistor (70) and a oscillator capacitor (72). An integrator (66) integrates an input voltage at a rate determined by an integrating resistor (64) and an integrating capacitor (68). The oscillator resistor (70) and integrator resistor (64) are designed such that their ratio will remain constant despite variations in actual value due to manufacturing inaccuracies. The oscillator capacitor (72) and integrating capacitor (68) are similarly designed. Consequently, an optimum peak integration value can be obtained at full scale input despite variations in actual resistive and capacitive values.

REFERENCES:
patent: 3316547 (1967-04-01), Ammann
patent: 3402372 (1968-09-01), Wasyluk
patent: 4020222 (1977-04-01), Kausche et al.
patent: 4063210 (1977-12-01), Collver
patent: 4502894 (1985-03-01), Seto et al.
patent: 4581795 (1986-04-01), Mobbs et al.
patent: 4704625 (1987-11-01), Lee

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