Integrated driver circuitry

Telephonic communications – Subscriber line or transmission line interface – For line length compensation

Reexamination Certificate

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Reexamination Certificate

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10153173

ABSTRACT:
A linear amplifier architecture includes first, second, and third stages. The first stage is a transconductance stage. The third stage is a current amplification stage. The second stage is an interfacing stage between the first and third stages. The interfacing stage provides a voltage bias and a current to the third stage. The linear amplifier is a class AB amplifier. Quiescent currents for the output devices of the third stage are controlled by the second stage. The stages may be fabricated on the same semiconductor substrate. In one embodiment, the amplifier is fabricated as a complementary metal oxide semiconductor (CMOS) integrated circuit using metal oxide semiconductor field effect transistors (MOSFET). In one application, the amplifier serves as a component of a driver circuit for a subscriber line. Electrostatic discharge (ESD) protection circuitry provided for the amplifier may also be suitable for other applications. In various embodiments, the ESD circuitry enables dynamic clamping of the output devices without introducing undesirable capacitive coupling during normal circuit operation.

REFERENCES:
patent: 5162753 (1992-11-01), Khorramabadi
patent: 5649009 (1997-07-01), Enriquez et al.
patent: 6166603 (2000-12-01), Smith
patent: 6249410 (2001-06-01), Ker et al.
patent: 6275102 (2001-08-01), Muza
patent: 6442255 (2002-08-01), Pitsch et al.
Haideh Khorramabadi, “A CMOS Line Driver with 80 dB Linearity for ISDN Applications”, IEEE Journal of Solid State Circuits, vol. 27, No. 4 p. 539-542 (Apr. 1992).
Fan You, et al., “Low Voltage Class AB Buffers with Quiescent Current Control”, IEEE Journal of Solid State Circuits, vol. 33, No. 6, p. 915-920 (Jun. 1998).

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