Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-03-03
2001-01-23
Chow, Dennis-Doon (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S206000, C349S140000
Reexamination Certificate
active
06177916
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relate to a flat panel display device, such as a liquid crystal display device and, in particular, an integrated driver circuit type liquid crystal display device in which an image display unit is integrated with a driver circuit on a common substrate.
2. Discussion of the Background
An integrated driver circuit type liquid crystal display device is a monolithic semiconductor formed on a glass substrate. The liquid crystal display device includes a plurality of scanning lines, a plurality of signal lines crossing the scanning lines at right angles to define cross points, pixel electrodes disposed in the vicinities of the cross points and, scanning and video signal driver circuits to supply scanning and video signals to the scanning and signal lines, respectively.
The signal driver circuit essentially has timing signal generators to control a timing thereof, a buffer circuit to amplify the timing signal from the timing circuits, video signal busses supplied with video signals from external equipment, and analogue switches for video signal distribution to sample the video signals of the video signal busses and transfer the same to the signal lines in response to outputs from the buffer circuits.
In a conventional integrated driver circuit liquid crystal display device, driving loads increase as the display size becomes larger and decreases an operation margin due to the higher definition bring about a poorer video signal bandwidth. In order to overcome those technical problems the analogue switches connected to a plurality of the signal lines are controlled in accordance with a common timing signal and a plurality of the video signal busses are provided to supply a different video signal to each analogue switch. As a consequence, permissible sampling periods become much longer than in the case that the analogue switches are individually controlled in accordance with different timing signals and video signals can be sufficiently sampled.
Since an allocated sampling time becomes shorter as the display size is larger and/or the display definition is higher, more analogue switches are controlled at same timing so that the number of video signal busses is apt to increase.
The area occupied by a signal bus driver circuit on a glass substrate becomes larger and the effective display area of a display device decreases in accordance with the increase of the number of prior art video signal busses.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an integrated driver circuit type liquid crystal display device which is capable of securing a sufficient video signal bandwidth without an increase of the area occupied by a signal line driver circuit.
According to the present invention, buffer circuits and analogue switches are disposed between video signal busses and signal lines in a video display region of an integrated driver circuit type liquid crystal display device. Further, control terminals at groups of the analogue switches are connected to the buffer circuits which, in turn, are commonly coupled to single output signal lines of the timing signal generator circuits, respectively. The analogue switches are also connected between video signal busses and signal lines in the video display region. The analogue switches distribute video signals of the video busses to the signal lines in a video display region in response to the sampling pulses supplied to the control terminals thereof from the timing signal generator circuits.
This structure minimizes the area in which the single output signal line only crosses the video signal busses in the case that the timing signal generator circuit is disposed outside the busses. Also, it is not necessary for the single output signal line to cross the busses and no crossing area is needed where the timing signal generator circuit is provided inside the busses. Those arrangements reduce parasitic or stray capacitance at the video signal busses and can provide the basses with sufficiently broad bandwidth characteristics.
The above-stated and other objects and advantages of the invention will become apparent from the following description when taken with the accompanying drawings. It is understood, however, that the drawings are for purposes of illustration and are not to be construed as defining the scope or limits of the invention, reference being had for the latter purpose to the claims appended hereto.
REFERENCES:
patent: 5841414 (1998-11-01), Tanaka
patent: 5945984 (1999-08-01), Kuwashiro
Aoki Yoshiro
Karube Masao
Chow Dennis-Doon
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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