Boots – shoes – and leggings
Patent
1994-10-04
1997-05-13
Pan, Daniel H.
Boots, shoes, and leggings
395290, 395306, 364DIG1, 364DIG2, G06F 926, G06F 940, G06F 944, G06F 1336
Patent
active
056301537
ABSTRACT:
An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.
REFERENCES:
patent: 3631405 (1971-12-01), Hoff et al.
patent: 4276594 (1981-06-01), Morley
patent: 4541048 (1985-09-01), Propster et al.
patent: 4594651 (1986-06-01), Jaswa et al.
patent: 4641238 (1987-02-01), Kneib
patent: 4799144 (1989-01-01), Parruck et al.
patent: 4811345 (1989-03-01), Johnson
patent: 4860191 (1989-08-01), Nomura et al.
patent: 4862407 (1989-08-01), Fette et al.
patent: 4876660 (1989-10-01), Owen et al.
patent: 4908825 (1990-03-01), Vea
patent: 4975947 (1990-12-01), Chauvel
patent: 4991169 (1991-02-01), Davis et al.
patent: 5005168 (1991-04-01), Cummiskey et al.
patent: 5029204 (1991-07-01), Shenoi et al.
patent: 5036539 (1991-07-01), Wrench, Jr. et al.
patent: 5045993 (1991-09-01), Murakami et al.
patent: 5111530 (1992-05-01), Kutaragi et al.
patent: 5155852 (1992-10-01), Murakami et al.
patent: 5185599 (1993-02-01), Doornink et al.
patent: 5208832 (1993-05-01), Greiss
patent: 5293586 (1994-03-01), Yamazaki et al.
MCS 8080/8085 Family User's Manual, Intel 1986, 5-1-19.
MCS 80/85 Family User's Manual, Intel Corporation, 1986, Chapter 5, The Instruction Set.
Electronic Design, Aug. 22, 1991, Microcontroller Eases Closed-Loop Servo Control, Dave Bursky, pp. 119-121.
National Semiconductor, Jan. 1990, NS32FX16-15/NS32FX-16-20/NS32FX16-25, High Performance FAX Processor.
Electronic Engineering Times, Aug. 26, 1991.; Ron Wilson: "Zilog Uses DSP for Disk Drive IC".
National Semiconductor, Jan. 11, 1989, KV96-X6D modem chip set.
"A Next-Generation 32 bit VLSI Signal Processor"; Shinjo Tsujimichi et al.; ICASSP 86, Tokio; 1986 IEEE; pp. 415-416.
Wescon Technical Papers, 30th Oct. 1984, pp. 4/3/1-7; Perlman: Bipolar and CMOS Technologies Become Partners in Dig. Sig. Processing.
IEEE Micro, vol. 6, No. 6, Dec. 1986, pp. 60-69; Eichen: "NEC'S mu PD77230 Digital Signal Processor".
Electronics, vol. 52, No. 26, Dec. 1979, pp. 109-115; Schirm: "Packing a signal processor onto a single digital board".
Texas Instruments, "TMS320C25 User's Guide Preliminary"; pp. 1/1-1/5, 2/1-2/21.
Doi et al., "A digital signal processor for modem applications", Electronic Engineer, Oct. 1989, pp. 198-204, 206.
Rockwell Preliminary Data Sheet, "R96DFX 9600bps Monofax Modem with Error Detection and DTMF Reception", Document #29200N60; Jul. 1989.
Yamaha Preliminary Data Sheet, "YM7109 MD96FX (9600bps Fax Modem LSI)", Catalog No.:LSI.
Reiner, et al.; "VLSI Development of a Global Memory Interface Controller"; pp. 0254-0257 (7.8.1.-7.8.4.); IEEE 1990.
Ruby B. Lee; "HP Precision: A Spectrum Architecture"; pp. 242-251; IEEE 1989.
Sorin Iacobovici; "A Pipelined Interface for High Floating-Point Performance with Precise Exceptions"; pp. 77-87; IEEE 1988.
Fotland et al.; "Hardware Design of the First HP Precision Architecture Computers"; pp. 4-17; Hewlett Packard Journal Mar., 1987.
R. Haines: "Two muCs on one chip split the silicon and the work": Electronic Design, vol. 29, No. 10, May 1981, pp. 197-202, Waseca, US.
L. Vieira et al.: "A multiprocessing system for the TMS32020": Microprocessing and Microprogramming: vol. 23, nos. 1-5, Mar. 1988, pp. 221-225 Amsterdam, NL.
M.C. Ertem: "A reconfigurable co-processor for microprocessor systems": Conference Proceedings of the IEEE Sourtheastcon '87:Tampa, Florida, 5th-8th, Apr. 1987, fol. 1, pp. 225-228, IEEE.
M. Homewood et al.: "The IMS T800 transputer": IEEE Micro, vol. 7, No. 5, Oct. 1987, pp. 10-26.
J.R. Schweitzer: "Design implementation and analysis of a modular digital signal processing system": 5th International Conference on Systems Engineering: Fairborn, Ohio, 9th-11th; Sep. 1987, pp. 447-450, IEEE, New York, US.
M.L. Fuccio et al: "The DSP32C: AT&T's second-generation floating-point digital signal processor": IEEE Micro, vol. 8, No. 6, Dec. 1988, pp. 30-47, IEEE, New York, US.
Doron Moshe
Epstein Lev
Greiss Israel
Intrater Amos
Intrater Gideon
National Semiconductor Corporation
Pan Daniel H.
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