Integrated digital multiplexer circuit

Details Integrated digital multiplexer circuit Integrated digital multiplexer circuit

1988-10-07

1989-05-30

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

307243, 3072992, 307455, H03K 1762

Patent

active

048357715

ABSTRACT:
A multiplexer module includes N input transistors (T.sub.0 to T.sub.3) whose bases receive input signals (E.sub.0 . . . E.sub.3), whose collectors are connected to ground and whose emitters are coupled to those of a multi-emitter output transister T'.sub.4. A logic addressing circuit (ALC) connects a current source I to one of the emitters of the input transistors (T.sub.0 to T.sub.3) as a function of an address (A.sub.0, A.sub.1) received. Any reference voltage on the output transistor (T'.sub.4) is suppressed by short-circuiting its base and its collector which constitutes the output S' which is connected to ground by way of an output resistor R'.sub.s. The module may be connected to other modules (having e.g. K inputs) within the same circuit, notably in order to realize a multiplexer having N.sup.k inputs without giving rise to stray coupling between the outputs of the various modules.

REFERENCES:
patent: 3539824 (1970-11-01), Yu et al.
patent: 3629610 (1971-12-01), Wilhelm
patent: 3925651 (1975-12-01), Miller
patent: 3984702 (1976-10-01), Fett
patent: 4191856 (1980-03-01), Nagano et al.
patent: 4616358 (1986-10-01), Rehm et al.
patent: 4621201 (1986-11-01), Amdahl et al.
patent: 4628216 (1986-12-01), Mazumder
"Sylvania Universal High-Level Logic", Brochure, Feb. 5, 1965, pp. 1-4.

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