Integrated digital loop carrier system with virtual...

Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels

Reexamination Certificate

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C370S509000, C370S466000

Reexamination Certificate

active

06333940

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an improved integrated digital loop carrier (IDLC) system which is integrated with a local digital switch (LDS) and which is provided with interface equipment capable of terminating a variety of different feeders. This invention also relates to a method of mapping and demapping signals between virtual tributaries (VT) and digital signals and to a circuit for performing the VT mapping functions.
BACKGROUND OF THE INVENTION
Because of the rapid evolution of telephone exchange equipment in the years since about 1980, a variety of types of transmission media exist in telephone exchanges throughout North America. On the other hand, because of the increasing demands for higher density and otherwise improved telephone systems, as well as for special features and services, there is increased impetus for still greater advances. A new system introduced today is ideally capable of high density service with data handling, as well as voice handling capability, and with provision for the special features and services that are becoming more common. Further, a new system should be able to interface with switch systems of the future, as well as those presently in service, including analog and digital systems.
Integrated digital loop carrier (IDLC) systems have been developed which use virtual tributary groups to facilitate data handling or organization. An IDLC system generally comprises a remote digital terminal (RDT), a local digital switch (LDS) having a high speed termination function, and a synchronous optical network (SONET) or DS1-based digital transmission facility connecting them. The SONET protocol for optical transmission data and voice is standardized at specified line rates designated in Megabits per second (Mbs). A first level, Optical Carrier level 1, or OC-1, transmits data at the rate of 51.84 Mbs. This carrier level has a corresponding electrical level (i.e., signals transported over wire versus optical fiber) called Synchronous Transport signal level 1, or STS-1. Higher levels of SONET carriers include OC-3 (155.52 Mbs), OC-6 (311.04 Mbs), OC-9 (466.56 Mbs) and OC-12 (622.08 Mbs).
In order to access a high frequency carrier such as an STS-1 signal, access products are required so that lower bandwidth carriers can be introduced into or extracted from the STS-1 signal. Access products provide a SONET network with nodes where components of an STS-1 signal can be added to or dropped out of the main signal. The components that are extracted must be reorganized to produce a signaling format compatible with currently used telephone standards. Components that are added must be reorganized for insertion into a SONET signal. A typical component of an STS-1 signal is a DS1 signal having a bit rate of 1.544 Mbs. Twenty-eight DS1 signals can be supported by an STS-1 signal. Twenty-four DS0 signals with a rate of 64 kbs can be supported within each DS1 signal.
An STS-1 SONET formatted signal comprises 810 bytes. The 810 bytes are organized in a frame structure comprising 9 rows by 90 columns of eight bit bytes that are serially transmitted row by row from left to right. The 27 bytes found in the first three columns of the frame are section and line overhead bytes. The payload is the 783 bytes found in the remaining 87 columns of the frame. Nine of the payload bytes that are arranged in a single column are allocated to path overhead. A Synchronous Payload Envelope (SPE) can begin anywhere within the 9 by 87 bytes allocated to payload, and typically begins in one SONET frame and ends in the next consecutive SONET frame. A payload pointer (i.e., H1 and H2 bytes contained in the line overhead) indicate the frame payload byte where the SPE begins.
Information within a SPE is transported in sub-STS payloads called virtual tributaries. A virtual tributary (VT) represents a portion of the total amount of data carried by an optical channel, or a portion of the total data capacity of the optical channel. A 27 byte structure, or 9 rows by 3 columns, of the SPE has a rate of 1.728 Mbs and can therefore accommodate a 1.544 Mbs DS1 signal. Accordingly, this particular VT is designated VT1.5. VTs of other sizes are similarly designated by a number following the initials, e.g., VT2, VT3 and VT6, which can accommodate CEPT-1 (2.048 Mbs), DS1C (3.152 Mbs) and DS2 (6.912 Mbs) signal payloads, respectively. Typically, 28 1.728 Mbs virtual tributaries or VT1.5s are embedded with overhead into an STS-1. Finally, the STS-1s are multiplexed with an overhead into the OC-3 (3 STS-1s) or OC-12 (12 STS-1s) signal.
As will be described, the present invention can, in accordance with an embodiment thereof, terminate VT1.5s and handle Floating Byte-Synchronous and Floating Bit-Asynchronous payload mapping, as required-by Bellcore Technical Reference TR-TSY-303. In the Floating VT mode, four consecutive 125 microsecond (&mgr;s) frames of the STS-1 SPE are organized into a 500-&mgr;s superframe, the phase of which is indicated by the Indicator byte (H4) in the STS path overhead (POH). This defines a 500-&mgr;s structure for each of the VTs, which is called the VT Superframe. The VT Superframe contains the VT Payload Pointer and the VT SPE. Four bytes of the VT Superframe are designated for VT Pointer use (V1, V2, V3, and V4, which is undefined). The remaining bytes define the VT Envelope Capacity, which is different for each VT size. The VT Payload Pointer provides for flexible and dynamic alignment of the VT SPE within the VT Envelope Capacity, independent of other VT SPEs.
In the Locked VT mode, the VT structure contains synchronous payloads that are “locked” to the STS-1 SPE. Because the tributary information is fixed and immediately identifiable with respect to the STS-1 Pointer, there are no VT pointers to process. Asynchronous mapping does not require frame acquisition and generation. Byte-synchronous mapping of synchronous DS1 signals, that is, DS1 signals whose timing is traceable to a common timing reference source, allows direct identification and access to the DS0 channels carried in the DS1s, and therefore requires frame acquisition and generation. A byte-synchronous DS0 interface places the 24 DS0 channels of a DS1 signal into the corresponding DS0 channel positions of a Locked VT1.5. The words “synchronous” and “asynchronous” will hereinafter be abbreviated as “sync” and “async”, respectively.
In the Floating Byte-Sync mode, the DS0s within the VT are accessed and aligned to the internal frame timing, and the VT1.5 path overhead bytes no longer required. In the Floating Bit-Async mode, the VT1.5 is passed intact transparently to channel units where it is processed.
SUMMARY OF THE INVENTION
An aspect of the present invention is a digital loop carrier system having increased bandwidth for each channel and the capability of providing a broader variety of services than existing equipment.
Briefly described, the present invention is a digital terminal for a telephone system comprising the combination of a plurality of digital line feeders and signal processor means connected to the feeders for receiving digital signals therefrom and for translating the digital signals into optical signals. The terminal comprises at least one channel unit shelf, the shelf comprising a plurality of channel units and first and second optical-electrical interface units for converting optical signals into electrical signals. First and second optical transmission signal conducting means are connected to the signal processor means for receiving therefrom and carrying the optical signals, the first optical signal conducting means being connected in a serial loop to the first optical-electrical interface unit and the signal processor means and the second optical signal conducting means being connected in a serial loop to the second optical-electrical interface unit and the signal processor means for delivering to the optical-electrical units the optical signals. A channel shelf processor is in each channel unit shelf for selectively delivering to individual ones of the channel units electr

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