Integrated device with voltage selector

Details Integrated device with voltage selector Integrated device with voltage selector

2001-03-29

2002-11-05

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S530000

Reexamination Certificate

active

06476664

ABSTRACT:

TECHNICAL FIELD
The present invention refers to an integrated device, in particular to a nonvolatile memory, with a voltage selector.
BACKGROUND OF THE INVENTION
As is known, the increasing demand for high-density nonvolatile memories has led to the design of nonvolatile memory structures having architectures with high storage capacity and high compactness; in particular, the most recent developments have evolved from a two-level architecture towards a multilevel architecture.
This increase in storage capacity has led to an increase in circuit complexity. In particular, a nonvolatile memory comprises a memory array receiving different voltages during the different operative steps, such as reading and programming. In nonvolatile memories with a two-level architecture (which will hereinafter be referred to as “two-level memories”), one reading voltage Vdd is supplied during reading, and one programming voltage Vpp is supplied during programming.
Nonvolatile memories with multilevel architecture (which will hereinafter be referred to as “multilevel memories”) instead require a larger number of voltages. In fact, multilevel memories need different voltage values for each one of reading and programming. In particular, for example, during reading, certain parts of the memory are supplied with the reading voltage Vdd or with a boosted voltage Vboost (generated by a charge pump), while during programming the reading voltage Vdd, the boosted voltage Vboost and/or the programming voltage Vpp are required.
During each of the above-mentioned steps, the memory array (generally fabricated using an N-channel CMOS technology) is supplied by a voltage transmitted through switches formed by PMOS transistors, preferred to NMOS transistors in that they transmit positive voltages free from voltage drops. Unfortunately, PMOS transistors require, during their operation, inverse biasing of the drain and source regions with respect to the substrate. In fact, direct biasing of the above-mentioned regions may determine an injection of currents into the substrate and, consequently, latch-up phenomenon (i.e., undesired turning-on of parasitic components).
In order to prevent latch-up, devices are used that at each instant bias the N regions, and in particular the substrates of the selectors, at the maximum potential fed to the PMOS transistor during each one of the different operative steps.
An example of a device for the selection of the highest voltage in a nonvolatile memory of a known type is described in EP-A-0 961 288.
This known device comprises two PMOS transistors. The PMOS transistors each receive on a first terminal two input voltages which, at least in certain operative conditions, may be different, and are connected to each other at a second terminal. A biasing circuit supplies the substrate of the PMOS transistors with the highest voltage among the input voltages.
The known integrated device has the drawback to be operative only within a limited voltage range. In particular, in the known integrated device, the reading voltage Vdd and programming voltage Vpp must be strictly greater than zero. In addition, a reading voltage Vdd having a value greater than 3 V and/or greater than Vboost cannot be used.
The integrated device described above has an unstable operation in the transient from Vpp to Vboost. In greater detail, when the programming voltage Vpp reaches the boosted voltage Vboost, the characteristics of some components of the integrated device vary, due to the presence of a positive feedback loop.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides an integrated device configured to select the highest voltage, from among such as may be available, to bias memory cells.
The integrated device comprises a PMOS transistor and a voltage selector having an output connected to the bulk terminal of the PMOS transistor. The voltage selector comprises an input stage supplying a supply voltage or a programming voltage according to whether the device is in a reading step or in a programming step. A comparator connected to the output of the input stage, receives a boosted voltage, and generates a first control signal, whose state depends upon the comparison of the voltages at the inputs of the comparator. A logic circuit is connected to the output of the comparator and generates a second control signal, the state whereof depends upon the state of the first control signal and of a third-level signal. A switching circuit is controlled by the first control signal, by the second control signal, and by the third-level signal and supplies each time the highest among the supply voltage, the boosted voltage, and the programming voltage.
The invention has many advantages, among them that parasitic latching is reduced, or prevented altogether. It also provides greater reliability in the storage and retention of data.


REFERENCES:
patent: 5003511 (1991-03-01), Secol et al.
patent: 6232827 (2001-05-01), De et al.
patent: 6252536 (2001-06-01), Johnson et al.
patent: 0322002 (1989-06-01), None
patent: 0961288 (1999-12-01), None
patent: WO96/23307 (1996-08-01), None

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