Integrated device with pads

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

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257773, 257784, H01L 2978

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active

059230762

ABSTRACT:
An integrated device having an N-type well region formed in a P-type substrate and an N.sup.+ type contact ring housed in the well region. The well region forms respective capacitors with a conductive layer superimposed on the substrate, and with the substrate itself. The conductive layer and the substrate are grounded, and the contact ring is connected to the supply, so that the two capacitors are in parallel to each other and, together with the internal resistance of the well region, form a filter for stabilizing the supply voltage. When connected to an input buffer stage of the device, the filter provides for damping the peaks produced on the supply line of the input buffer by high-current switching of the output buffers.

REFERENCES:
patent: 4710791 (1987-12-01), Shirato et al.
European Search Report from European Patent Application 96830095.4, filed Mar. 6, 1996.
Patent Abstracts of Japan, vol. 014, No. 396 (E-0970), Aug. 27, 1990 & JP-A-02 148845 (Hitachi Ltd.).
Patent Abstracts of Japan, vol. 012, No. 489 (E-696), Dec. 21, 1988 & JP-A-63 204755 (NEC Corp.).
Patent Abstracts of Japan, vol. 011, No. 130 (E-502), Apr. 23, 1987 & JP-A-61 274352 (Fujitsu Ltd.).
Patent Abstracts of Japan, vol. 015, No. 094 (E-1041), Mar. 6, 1991 & JP-A-02 304963 (NEC Corp.).
Patent Abstracts of Japan, vol. 014, No. 518 (e-1001), Nov. 14, 1990 & JP-A-02 216862 (NEC Corp.).

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