Integrated device structure prediction based on model curvature

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system

Reexamination Certificate

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C703S001000, C703S002000, C716S030000, C716S030000

Reexamination Certificate

active

06643616

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to structure modeling and prediction. More specifically, the invention relates to predicting a physical structure, for example, integrated circuit structures, based on information derived from contour representations.
BACKGROUND OF THE INVENTION
As integrated circuits (ICs) become more dense, the widths of lines and components, as well as the separation between lines becomes increasingly smaller. Currently, deep sub-micron (<0.25 &mgr;m) processes are being used. However, with deep sub-micron processes, silicon yield is affected by several factors including reticle/mask pattern fidelity, optical proximity effects, and diffusion and loading effects during resist and etch processing. Typical problems include line-width variations that depend on local pattern density and topology and line end pullback.
Optical and process correction (OPC) can be used to improve image fidelity. Optical proximity correction is a subset of optical and process correction. OPC techniques include, for example, introduction of additional structures to the IC layout that compensate for various process distortions. Two general categories of OPC are currently in use: rule-based OPC and model-based OPC. In rule-based OPC, a reticle layout is modified according to a set of fixed rules for geometric manipulation. However, rule-based OPC has limited capability and when more complex OPC is desired, model-based OPC is used.
In model-based OPC, an IC structure to be formed is modeled and a threshold that represents the boundary of the structure on the wafer can be determined from simulated result generated based on the model used. Simple forms of model-based OPC generate a simulated aerial image, I(x, y), having a threshold, I
th
, to predict the structure to be manufactured.
A more sophisticated and accurate model-based OPC technique, referred to as the Variable Threshold Resist (VTR) model, allows the threshold, I
th
, to take on multiple values. The VTR model is described by Cobb, et al., “Mathematical and CAD Framework for Proximity Correction,” Optical Microlithography IX, Proc. SPIE 2726, pp. 208-222 (1996); Cobb, et al., “Experimental Results in Optical Proximity Correction with Variable Threshold Resist Model,” Optical Microlithography X, SPIE 3051, pp. 458-468 (1998); and Nicholas B. Cobb, “Fast Optical and Process Proximity Correction Algorithms for Integrated Circuit Manufacturing,” PhD dissertation, Univ. Cal. Berkeley (1998).
FIG. 1
is one embodiment of contours representing an integrated circuit line end based on a Variable Threshold Resist (VTR) model. In general, the VTR model is used to determine characteristics of the integrated circuit structure where the threshold,
I
th
=
f

(
I
max
,

I

x

|
max
)
,
is a function of two variables, maximum intensity, I
max
, and maximum slope,

I

x
&RightBracketingBar;
max
,
as measured along a one-dimensional cut-line through the x-axis of the simulated result. As illustrated in
FIG. 1
, the x-axis orientation is parallel to one of the axes used in the integrated circuit layout. The slope determined from the simulated result can be used to modify the design of the integrated circuit.
The VTR model has been used to provide improved IC manufacturing; however, for certain situations, for example, line-end shortening, rule-based OPC can still provide better correction. Therefore, it is desirable to have an improved model-based OPC model.
SUMMARY OF THE INVENTION
Methods and apparatuses for structure prediction based on model curvature are described. A predicted curvature for a structure to be realized is determined. The structure can be, for example, an integrated circuit structure on a layer of an integrated circuit. The predicted curvature is used to determine a predicted boundary of the structure. Based on the predicted boundary of the integrated circuit structure to be realized, the layout of the integrated circuit structure can be modified.


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