Integrated device combining a bipolar transistor and a field eff

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

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257256, 257265, H01L 2980, H01L 29808

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active

054882419

ABSTRACT:
An integrated device combines a bipolar transistor (10) and a junction field effect transistor (12) so as to produce an output voltage (Vd) which is higher than the breakdown voltage (BV.sub.CEO) of the bipolar transistor (10). A lateral extension (30) of the base zone (28), which forms a gate, is provided with an opening (38) in which a drain region (40) of the field effect transistor is situated. A heavily doped peripheral region (36) of the same type as the drain region (40) surrounds the lateral extension (30) on three sides, while a heavily doped buried layer region (34), which forms a conductive part of the collector of the bipolar transistor (10), extends to below the peripheral region (36) and forms with the latter the source of the field effect transistor (12). The resulting device has substantially improved breakdown voltage characteristics.

REFERENCES:
patent: 3578514 (1971-05-01), Lesk
patent: 4485392 (1984-11-01), Singer
patent: 4729008 (1988-03-01), Beasom
patent: 4739386 (1988-04-01), Tanizawa
patent: 4808547 (1989-02-01), Beasom
patent: 4835596 (1989-05-01), Werner
patent: 4987469 (1991-01-01), Ludikhuize
"Improving Performance of Transistors" by D. C. Wyland, IBM Technical Disclosure Bulletin, vol. 13, No. 1, Jun. 1970, p. 204.
"500 V BIMOS Technology and its Applications", 16th Annual IEEE Power Electronics Conference, Toulouse, Jun. 1985 by E. Wildi et al.

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