Integrated delay line calibration method and apparatus for direc

Details Integrated delay line calibration method and apparatus for direc Integrated delay line calibration method and apparatus for direc

1998-10-06

2000-09-19

Le, Dinh T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327244, 327243, 360 65, 375371, H03H 1126

Patent

active

061218103

ABSTRACT:
An integrated delay line calibration method and apparatus are provided for a direct access storage device (DASD). A delay line, such as used in a direct access storage device (DASD) is calibrated by configuring the delay line as a ring oscillator for calibration. A delay line ring frequency is compared to a reference frequency. The delay of the delay line is adjusted until the delay line ring frequency and the reference frequency are equal. Each delay block within the delay line is controlled by a delay adjust digital-to-analog converter (DAC). A control logic circuit couples N-bit words to the delay adjust digital-to-analog converter (DAC) for calibration adjustment of the delay line delay.

REFERENCES:
patent: 5087842 (1992-02-01), Pulsipher et al.
patent: 5382921 (1995-01-01), Estrada et al.
patent: 5396130 (1995-03-01), Galbraith et al.
patent: 5696951 (1997-12-01), Miller
patent: 5878097 (1999-03-01), Hase et al.

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