Integrated delay line

Details Integrated delay line Integrated delay line

1991-12-30

1993-09-14

Ng, Jin F.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307602, 307269, 328 63, H03K 513

Patent

active

052452310

ABSTRACT:
A delay line within an integrated circuit and calibrated by an external time period (calibration clock). The speed of devices in the integrated circuit is assessed using the calibration clock, and this speed then controls how many delay cells within the delay line an input must traverse to trigger the delayed output.

REFERENCES:
patent: 3588707 (1971-06-01), Manship
patent: 4675612 (1987-06-01), Adams et al.
patent: 4713621 (1987-12-01), Nakamura et al.
patent: 4845390 (1989-07-01), Chan
patent: 4868514 (1989-09-01), Azevedo et al.
patent: 5087842 (1992-02-01), Pulsipher et al.

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