Integrated delay circuit with PN-junction capacitor

Details Integrated delay circuit with PN-junction capacitor Integrated delay circuit with PN-junction capacitor

1979-12-12

1981-11-24

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307557, 307605, 357 51, H03K 513

Patent

active

043026915

ABSTRACT:
In an integrated silicon circuit a PN junction capacitor is charged to almost the full DC power supply voltage through a resistor and through the base-emitter junction of an output transistor. A constant current source and an input transistor switch are simultaneously turned on to dicharge the capacitor at a constant rate, the output transistor being held off until the capacitor is almost fully discharged. The delay, from the time of turning on the constant current source to the time the output transistor turns on, is substantially independent of severe drops in power supply voltage that may occur during this delay period.

REFERENCES:
patent: 3358236 (1967-12-01), Weber
patent: 3543091 (1970-11-01), Marek
patent: 4047057 (1977-09-01), Ahmed

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