Integrated debug trigger method and apparatus for an integrated

Details Integrated debug trigger method and apparatus for an integrated Integrated debug trigger method and apparatus for an integrated

1996-11-14

1998-05-12

Beausoliel, Jr., Robert W.

Excavating

39518306, G06F 1127

Patent

active

057517355

ABSTRACT:
Presented is an internal integrated debug trigger apparatus for use in debugging functional and electrical failures of an integrated circuit chip. The debug trigger apparatus includes a plurality of software programmable trigger registers and a plurality of software programmable trigger function blocks. Each trigger register monitors a plurality of integrated circuit signals which may include signals sent to the external pins of the integrated circuit and signals present internal to the chip. If the value of the monitored signals matches the programmed trigger condition, the trigger register produces a trigger match signal. Each trigger function block receives a combination of the trigger match signals generated by the trigger registers and each computes its programmed boolean minterm function on its inputs. Each trigger function block produces a trigger capture signal which may be true or false according to the computed function of the inputs. The debug trigger may also include a programmable iteration counter which allows for repetition of a trigger condition before it is provided external to the chip. The output of the iteration counter may be connected as input to one or more of the other trigger registers to allow for different start and end conditions.

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