Multiplex communications – Wide area network – Packet switching
Patent
1990-03-15
1992-06-09
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 851, 370 84, 364DIG1, 364DIG2, 395200, 395275, H04J 324
Patent
active
051213907
ABSTRACT:
A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.
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Farrell Joseph K.
Gordon Jeffrey S.
Jenness Robert V.
Kuhl Daniel C.
Lee Timothy V.
Brown, Jr. Winfield J.
International Business Machines - Corporation
Lieber Robert
Olms Douglas W.
Ton Dang
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