Integrated data input sorting and timing circuit for double...

Details Integrated data input sorting and timing circuit for double... Integrated data input sorting and timing circuit for double...

2000-03-16

2004-05-25

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060, C365S230080

Reexamination Certificate

active

06741520

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit double data rate (“DDR”) dynamic random access memory (“DRAM”) devices. More particularly, the present invention relates to an integrated data input sorting and timing circuit for DDR DRAM memory devices.
Historically, in order to synchronize data transfers among system logic devices, data transfers, to/from conventional DRAM devices would be initiated on either the rising (the transition from logic level “zero” to “one”) or falling (the transition from logic level “one” to “zero”) edge of a clock signal. DDR DRAM memory devices differ from conventional DRAM by enabling output operations to occur on both the rising and falling edges of the clock, thereby effectively doubling the device's output frequency without increasing the actual clock frequency.
For certain DDR DRAM device specifications, at least two specific problems have been identified pertaining to write cycles. Firstly, data is gathered on the rising and falling edge of the DQS strobe (or multiple strobes in, for example, x
16
memory devices), but the rising edge can correspond to either a condition CO=0 or condition CO=1. The falling edge data is then the opposite, where CO is the A∅ address at column time. Each successive write cycle can switch between CO=0 (even start) or CO=1 (odd start). Secondly, the position of the DQS strobe relative to the system clock can have up to a 25% shift. However, as a practical matter a good design must be able to tolerate a much larger skew than the specification value so as to provide sufficiently ample operating margin.
SUMMARY OF THE INVENTION
In accordance with the present invention, the sorting of the input data into odd/even in a DDR DRAM memory device is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits to handle the odd/even sorting function and synchronization to the Y-clock function.
For cases with multiple DQS inputs (e.g., DQS(
0
:
1
)), any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data +{fraction (
1
/
2
)}) while conventional approaches may, in fact, write at a later time in an attempt to solve the foregoing issues.
In operation, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS. Rising edge data (“Redat (
0
:
1
)”) signals produced as disclosed herein, then specify whether the rising edge data should be mapped to the even (
0
) or odd field (
1
), with falling edge data being directed to the opposite field. The timing of the Redat signals is such that the internal odd and even data buses (G-buses) only transition prior to a given write clock (“Yw-clock”), and don't transition during the write clock itself. This is supported over a large range of positive (+) and negative (−) DQS-to-clock skews. Another Redat pair (
0
:
1
) is added for each additional DQS signal. As previously mentioned, there is no restriction on DQS-DQS skew, only DQS-CLK.
Briefly, disclosed herein is a method for handling data in an integrated circuit memory device comprising the steps of: capturing the data on opposite first and second transitions of a data strobe signal; selectively mapping the data captured on the first transition of the data strobe signal to a first data path and the data captured on the second transition to a second data path; latching the data on the first and second data paths when an internal write clock signal is active; and passing the data on the first and second data paths to respective internal output nodes when the internal write clock signal is not active.
Further disclosed herein is an integrated circuit memory device having a synchronizing clock signal and including a plurality of external data input paths. The memory device comprises a write data sort circuit for loading data applied to the external data input paths on a first transition of the synchronizing clock signal to either a first or second internal data path and alternatively loading data applied to the external data input paths on a second opposite transition of the synchronizing clock signal to the opposite one of the first or second internal data paths. The memory device further comprises a data-in sort clock circuit for operatively controlling the write data sort circuit and receiving the synchronizing clock signal and a data strobe signal for causing the write data sort circuit to latch the data on the first and second data paths when an internal write clock signal is active and to pass the data on the first and second data paths to respective internal output nodes when the internal write clock signal is not active.
Still further disclosed is a double data rate memory device comprising a write data sort circuit coupled to receive a first plurality of parallel data bits on a first internal data path on a rising edge of a data strobe clock and a second like plurality of parallel data bits on a second internal data path on a falling edge of the data strobe clock. The write data sort circuit is operative in association with a data-in sort clock circuit for selectively mapping the first plurality of parallel data bits to one of an even or odd data field and alternatively mapping the second plurality of parallel data bits to an opposite one of the even or odd data fields.
Also disclosed is a double data rate memory device comprising a data-in sort clock circuit coupled to an internal write clock of the memory device, the data-in sort clock circuit in operative association with a write data sort circuit to enable even and odd data fields stored therein to be applied to respective internal output nodes when the internal write clock is in a first state thereof and to alternatively disable application of the even and odd data fields to the respective internal output nodes when the internal write clock is in a second opposite state thereof.


REFERENCES:
patent: 5610862 (1997-03-01), Teel
patent: 5978281 (1999-11-01), Anand et al.
patent: 6034916 (2000-03-01), Lee
patent: 6081477 (2000-06-01), Li
patent: 6091663 (2000-07-01), Kim et al.
patent: 6101612 (2000-08-01), Jeddeloh
patent: 6134180 (2000-10-01), Kim et al.

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