Integrated data and timing circuitry for automatic circuit teste

Details Integrated data and timing circuitry for automatic circuit teste Integrated data and timing circuitry for automatic circuit teste

1988-04-04

1990-02-13

Smith, Jerry

Excavating

G06F 1100

Patent

active

049013157

ABSTRACT:
An automatic circuit tester (10) applies signals to tester terminals (12a, b, and c) by means of corresponding data channels (14a, b and c). Each channel includes a leading-edge memory 18 and a trailing-edge memory 20 that provide outputs of successive locations upon the occurrences of clock pulses applied by a clock 16 through respective phase shifters (22 and 24). A formatter (26) applies signals in accordance with the outputs of the memories (18 and 20) with a timing format determined directly by the times at which the memory outputs occur; no separate timing information is required by the formatters. The timing results from the phase shifts imposed by phase shifters 22 and 24 and by transitions in the contents of a plurality of successive memory locations provided for each period of the device under test.

REFERENCES:
patent: 4450560 (1984-05-01), Conner
patent: 4451918 (1984-05-01), Gillette
patent: 4517661 (1985-05-01), Graf
patent: 4730318 (1988-03-01), Bogholtz
patent: 4788684 (1988-11-01), Kawaguchi
patent: 4806852 (1989-02-01), Swan

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