Integrated content addressable memory architecture

Details Integrated content addressable memory architecture Integrated content addressable memory architecture

2003-04-22

2004-11-16

Tran, M. (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S190000

Reexamination Certificate

active

06819579

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates to an integrated content addressable memory (CAM) architecture, and more particularly, to an integrated CAM architecture based on a plurality of novel ten-transistor (10-T) CAM cells combined with a valid bit cell, a protect bit cell, and at least a mask cell coupled to a plurality of associated 10-T CAM cells.
2. Description of the Prior Art
Most memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory accesses. The time required to find an item stored in memory can be reduced significantly if the item can be identified for access by its content rather than by its address. A memory that is accessed in this way is called content-addressable memory (CAM). Briefly speaking, the basic feature of the CAM can be treated as a standard storage system, as a random access memory (RAM) device, combined with a comparison apparatus. Therefore, the CAM is an outgrowth of RAM technology and provides a performance advantage over other memory search structures. The CAM can be used to accelerate any application requiring fast searches of database, lists, or patterns, such as in image, voice recognition, or computer and communication designs. The CAM is also ideally suited for several functions, including data process of the computer's central processing unit (CPU), Ethernet address lookup, data compression, search engines, pattern recognition for encryption/decryption and compression/decompression applications, and so on.
Conventional content addressable memory (CAM) cells have been implemented primarily with static random access memory (SRAM) cells and arranged in rows and columns. The SRAM-based CAM cells have received widespread use due to the high access speed of SRAM memory cells and the static nature of the cells. With the above-mentioned characteristics of the CAM, in addition to SRAM functions of writing and storing data, the CAM also searches and compares the stored data to determine if the data match a set of compared data (search data) applied to the memory. When the newly applied compared data (search data) match the data already stored in the memory, a match result is indicated, whereas if the search and stored data do not match, a mismatch result is indicated. Please refer to
FIG. 1
, which is schematic diagram of a typical CAM architecture
10
arranged with a plurality of rows
10
A to
10
K. As shown in
FIG. 1
, each row (
10
A to
10
K) is coupled to a corresponding match line
12
(
12
A to
12
K) for indicating whether the compared data match the data stored in the row. The compared data and the previously stored data are all N-bit digital data in the present embodiment. Take row
10
A as instance, when the N-bit compared data are totally the same as the N-bit data stored in the row
10
A of the CAM architecture
10
, the corresponding match line outputs a logic high. On the contrary, when any data bit of the N-bit compared data is opposite to a corresponding data bit of the N-bit data stored in the row of the CAM architecture
10
, the corresponding match line changes to output a logic low.
Please go on referring to FIG.
1
. Previous approaches regarding data-comparing operation in a row of the CAM architecture
10
include a mask cell
15
(
15
A to
15
K) being coupled to a plurality of associated CAM cells. The comparing operations of the associated CAM cells are then either enabled or disabled by the mask cell
15
(
15
A to
15
K) content. For instance, the mask cell
15
A in the row
10
A are connected to the associated CAM cells
10
A(
2
) and
10
A(
3
), and the associated CAM cells
10
A(
2
) and
10
A (
3
) can be masked out by the mask cell
15
A. Examples of such implementation are also illustrated in U.S. Pat. No. 6,154,384, “Ternary content addressable memory cell” issued to Nataraj et al. and U.S. Pat. No. 6,108,227, “Content addressable memory having binary and ternary modes of operation” issued to Voelkel. Usually the associated CAM cells will be masked out from the comparing operations when the mask cell is asserted, and not be masked out from the comparing operations when the mask cell is de-asserted.
Each row (
10
A to
10
K) comprises a plurality of (binary) CAM cells. For instance, the row
10
A comprises N CAM cells
10
A(
1
) to
10
A(N). Each CAM cell is able to store a digital data value having two states of information: a logic one state and a logic zero state. As shown in
FIG. 1
, the N-bit data stored in each row (
10
A to
10
K) consist of N digital data value stored in corresponding N (binary) CAM cells. Please refer to
FIG. 2
, which is a schematic diagram of a (binary SRAM-based) prior-art CAM cell
20
in a row of the CAM architecture
10
as shown in FIG.
1
. Taking the row
10
A shown in
FIG. 1
for instance, the CAM cell
20
as shown in
FIG. 2
can correspond to each of the CAM cells
10
A(
1
) to
10
A(N) in the row
10
A. The CAM cell
20
includes a SRAM cell
26
, a comparator module
24
, and a match line
22
. The comparator module
24
compares the digital data value stored in the SRAM cell
26
with an input data value. When the input data value is the same as the digital data value stored in the SRAM cell
26
, the match line
22
will stay at the pre-charged high level. When the input data value is opposite to the digital data value stored in the SRAM cell
26
, the match line
22
will be pulled to a low potential. The CAM cell
20
further includes a word line
28
, a first bit line
30
, and a second bit line
32
, wherein the SRAM cell
26
and the comparator module
24
both share the first and the second bit line
30
,
32
. Moreover, please refer to both FIG.
1
and
FIG. 2
, if the CAM cell
20
is in the row
10
A and connected to the mask cell
15
A as shown in
FIG. 1
, the CAM cell
20
becomes a mask-able CAM cell
20
that effectively store three states of information, namely: a logic one state, a logic zero state, and a don't care state for comparing operations. The design of mask-able CAM cells offer more flexibility for users to determine on a row-per-row (entry-per-entry) basis whose partial bits will be masked out during a comparing operation.
For detailing the prior-art embodiment as shown in
FIG. 2
, please refer to
FIG. 3
, which is a schematic diagram of a detailed embodiment of the CAM cell
20
. The CAM cell
20
is a ten-transistor (10-T) CAM cell
20
, which indicates that the SRAM cell
26
is a six-transistor (6-T) SRAM cell
26
and the comparator module
24
is a four-transistor (4-T) comparator module
24
. During the practical implementation, the match line
22
will be pre-charged to a predetermined high potential before any comparison between the input data value and the digital data value stored in the 6-T SRAM cell
26
. However, due to that the 6-T SRAM cell
26
and the 4-T comparator module
24
share the same first and the second bit line
30
and
32
, the pre-charged potential of the match line
22
may be disturbed by the initial state of any other node in the 6-T SRAM cell
26
or the 4-T comparator module
24
as a node N
1
. In addition, the pre-charged potential of the match line
22
could be pulled down by the charge sharing between the match line
22
and the internal nodes as the node N
1
, and the voltage drop at the match line
22
depends on the capacitance related to the match line
22
and the internal nodes. All the above-mentioned effects of the prior art will be disadvantageous to the widely applied low-power operations.
In addition, for complying with the trend of integration of multiple functions in one electronic apparatus, it is desirable to keep CAM architecture as powerful as possible without increasing in each cell size that can translate into substantial increases in overall CAM architecture. Therefore, there is a need for developing a novel SRAM-based CAM cell and an integrated CAM architecture that achieve more efficient and sufficient alternatives,

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