Patent
1996-01-23
1998-09-01
Bowler, Alyssa H.
395309, 395310, 395872, 395562, 395563, 39580041, G06F 15173
Patent
active
058022880
ABSTRACT:
This document describes a feature that can be added to existing pipelined architectures (such as RISC) to enhance packet based or message passing communications. The feature integrates the communication interface directly into the pipeline of the processor, offering the potential to greatly reduce latency and overhead for fine grain communications. Additionally, a second interface is provided to maintain high bandwidth for large blocks of data.
REFERENCES:
patent: 4701845 (1987-10-01), Andreasen et al.
patent: 4907232 (1990-03-01), Harper et al.
Hamacher et al., Computer Organization, McGraw Hill, 1990, pp. 153, 220-221.
Tabak, RISC Systems, Research Studies Press Ltd., 1990, pp. 44-47.
Prohofsky, "High Speed Data Bus Macro Instruction Set Architecture," IEEE, 1991 pp. 192-196.
Ekanadham Kattamuri
Mraz Ronald
Bowler Alyssa H.
Cameron, Esq. Douglas W.
Follansbee John
International Business Machines - Corporation
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