Integrated code and data flash memory

Details Integrated code and data flash memory Integrated code and data flash memory

2007-01-02

2007-01-02

Phan, Trong (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280, C365S185290, C365S185330

Reexamination Certificate

active

10815370

ABSTRACT:
A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

REFERENCES:
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 5270969 (1993-12-01), Iwahashi
patent: 5424569 (1995-06-01), Prall
patent: 5448517 (1995-09-01), Iwahashi
patent: 5515324 (1996-05-01), Tanaka
patent: 5644533 (1997-07-01), Lancaster et al.
patent: 5699298 (1997-12-01), Shiau et al.
patent: 5768192 (1998-06-01), Eitan
patent: RE35838 (1998-07-01), Momodomi et al.
patent: 5815441 (1998-09-01), Kobatake
patent: 5937424 (1999-08-01), Leak et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6172907 (2001-01-01), Jenne
patent: 6215148 (2001-04-01), Eitan
patent: 6370062 (2002-04-01), Choi
patent: 6436768 (2002-08-01), Yang et al.
patent: 6458642 (2002-10-01), Yeh et al.
patent: 6487114 (2002-11-01), Jong et al.
patent: 6490196 (2002-12-01), Hsu et al.
patent: 6566699 (2003-05-01), Eitan
patent: 6614694 (2003-09-01), Yeh et al.
patent: 6643181 (2003-11-01), Sofer et al.
patent: 6671209 (2003-12-01), Lin et al.
patent: 6690601 (2004-02-01), Yeh et al.
patent: 6826084 (2004-11-01), Wong
patent: 6829175 (2004-12-01), Tsal et al.
patent: 6917544 (2005-07-01), Maayan et al.
patent: 2002/0172075 (2002-11-01), Park et al.
patent: 2002/0179958 (2002-12-01), Kim
patent: 2003/0137873 (2003-07-01), Kawamura
patent: 2003/0185055 (2003-10-01), Yeh et al.
patent: 2004/0027856 (2004-02-01), Lee et al.
patent: 2004/0042295 (2004-03-01), Fujiwara et al.
patent: 2004/0071030 (2004-04-01), Goda et al.
patent: 2005/0237809 (2005-10-01), Shih et al.
patent: 1 063 652 (2000-12-01), None
patent: 09162313 (1997-06-01), None
patent: 11233653 (1999-08-01), None
patent: 2004-039866 (2004-02-01), None
Bloom, Ilan, et al., “2-Bit Cell NV Memory Minimizes Chip Area with Less Masks,” Nikkei Electronics Asia, Jan. 2002, 11 pages.
De Blauwe, Jan, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transactions on Nanotechnology, vol. 1, No. 1, Mar. 2002, 72-77.
Hirose, M., “Challenges for Future Semiconductor Development,” International Microprocess and Nanotechnology Conference, Nov. 6, 2002, 47 pages.
Lee, Jae-Duk, et al., “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, vol. 23, No. 5, May 2002, 264-266.
Shin, Yoocheol, et al., “High Reliable SONOS-type NAND Flash Memory Cell with A12O3 for Top Oxide,” Non-Volatile Semiconductor Memory Workshop, 2003, 2 pages.
Lee, Changhyun, et al., “A Novel Structure of SiO2/SiN/High k Dielectrics, A12O3 for SONOS Type Flash Memory,” Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials, Nagoya, Japan, 2002, 162-163.
Yeh, C.C., et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” IEEE IEDM, 2002, 931-934.
Prinz, E.J., et al., “An Embedded 90nm SONOS Flash EEPROM Utilizing Hot Electron Injection Programming and 2-Sided Hot Hole Injection Erase,” NVM Workshop 2003, 2 pages.
Ruden, P. Paul, et al., “Modeling of band-to-band tunneling transitions during drift in Monte Carlo transport simulations,” J. Appl. Phys., vol. 88, No. 3, Aug. 1, 2000, 1488-1493.
Lee, Chang Hyun, et al., “A Novel SONOS Structure of SiO2/SiN/A12O3 with TaN Metal Gate for Multi-Giga Bit Flash Memeries,” IEEE 2003, 4 pages.
Chung, Steve S., et al., “A Novel Leakage Current Separation Technique in a Direct Tunneling Regime Gate Oxide SONOS Memory Cell,” IEEE 2003, 4 pages.
Swift, C.T., et al., “An Embedded 90nm Sonos Nonvolatile Memory. . . ” IEDM 2002, Dec. 8-11, 2002, 927-930.
She, Min, et al., “Silicon-Nitride as a Tunnel Dielectric. . . ” IEEE Electron Device Letters 24(5), May 2003, 3 pages.
Kim, Byungcheul, et al., “A Scaled Sonos Single-Transistor. . . ” J. Korean Phys. Soc. 41(6), Dec. 2002, 945-948.

Affiliated with

Also associated with

Rating

Integrated code and data flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated code and data flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated code and data flash memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3783581