Integrated CMOS circuit

Details Integrated CMOS circuit Integrated CMOS circuit

1998-04-27

1999-11-02

Kim, Jung Ho

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327545, 361 88, 365228, G05F 110

Patent

active

059778156

DESCRIPTION:

BRIEF SUMMARY
The invention relates to a CMOS circuit integrated in a semiconductor substrate comprising a principal circuit part, which contains the major part of the circuit elements in a well isolated from the substrate by a substrate diode, with a power output stage for driving an inductive load.
It is known that the so-called latch-up effect can occur in integrated CMOS circuits, which means that a parasitic thyristor structure, inherent in the design of the circuit, is fired by a current flowing through the substrate diode in the forward direction and accordingly changes into the conducting state, which can not be reversed without turning off the operating voltage. In particular firing of such thyristor structure is caused if the inductive load supplied by the CMOS circuit is turned off and the counter-EMF produced during such turning off operation results in there being a current flowing in the forward direction of the substrate diode. This current will fire the parasitic thyristor so that even after decay of the current caused by the inductive load a current will still flow through this thyristor from the supply terminal to ground. This latch-up effect is for example described in the book "Electronic und Microelectronic" by D. Sautter and H. Weinerth published by VDI Verlag 1993, page 559. Up till the present attempts have been focussed on preventing the occurrence of the latch-up effect with the aid of process related measures. Such process-related measures do however lead to an undesired increase in the surface area requirement of the circuit on its semiconductor chip. This additional area can however only be made available by the use of a larger chip, which leads to higher costs.
U.S. Pat. No. 5,212,616 discloses a latch-up protection circuit which prevents damage to a CMOS integrated circuit chip having internal circuitry due to transient surges or internal-circuitry initiated latch-ups. The latch-up protection circuit is integrated with an on-chip voltage regulation circuit which provides on-chip power to the internal chip circuitry. The on-chip voltage supplied to internal chip circuitry is compared by detection circuitry with a reference voltage signal representative of the occurrence of a latch-up condition, i.e., with the nominal external power supply. When the on-chip power supply voltage becomes lower than the trigger voltage, then a power transistor and the voltage regulation circuit are disabled by the detection circuitry, thereby reducing the latch-up condition.
In Patent Abstracts of Japan, vol. 12, no. 368 (P-766) (JP 63118848) a resetting circuit for abnormal case (e.g. latch-up state) of a microcomputer is described. After detecting a latch-up state the resetting circuit turns off a switch for a fixed period of time to stop the supply of power to the microcomputer, to the circuits associated with the microcomputer, and to a nonvolatile memory which is connected to the microcomputer. The data obtained before the microcomputer becomes abnormal can be extracted out of the nonvolatile memory.
U.S. Pat. No. 4,952,998 describes an integrated CMOS circuit having a transistor located in a p (or an n) well and an adjacent complementary transistor. The transistors are located in an epitaxial layer on a highly doped substrate. A "latch-up" can be avoided by providing under the source zone of the transistor located beside the well a second region having substantially the same doping and depth as the well, which is connected to the source zone.
One object of the invention is to provide an integrated CMOS circuit of the type initially mentioned, in which the latch-up effect is prevented with the aid of circuit-related measures.
In accordance with the invention this object is achieved by a CMOS circuit integrated in a semiconductor substrate comprising a principal circuit part, which contains the major part of the circuit elements in a well isolated from the substrate, and a power output stage driving an inductive load, characterized by a switching signal when it detects at the output a voltage biasing the su

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patent: 5761144 (1998-06-01), Fukuzumi
patent: 5901096 (1999-05-01), Inokuchi et al.

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