Integrated clock driver circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307480, 307475, 328 63, 328 72, H03K 513, H03K 1900

Patent

active

051110636

ABSTRACT:
An integrated circuit comprises a first clock driver responsive to an external clock signal and producing a first clock signal, a second clock driver responsive to the first clock signal and producing a second clock signal delayed from the first clock signal, an internal circuit responsive to the second clock signal and producing an output data signal, and an output circuit coupled to a data output pin and transferring the output data signal to the data output pin in synchronization with the first clock signal, so that a time interval between the production of the output data signal and the validity at the data output pin is shrunk even though a large parasitic capacitance is coupled to the data output pin.

REFERENCES:
patent: 4438404 (1984-03-01), Philipp
patent: 4529895 (1985-07-01), Garverick et al.
patent: 4618786 (1986-10-01), Johnson
patent: 4816700 (1989-03-01), Imel
patent: 4929854 (1990-05-01), Iino et al.
patent: 4933571 (1990-06-01), Pribyl

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