Integrated clock drive circuit

Details Integrated clock drive circuit Integrated clock drive circuit

1977-06-09

1978-09-26

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307232, 328139, 307352, H03K 117

Patent

active

041173520

ABSTRACT:
A buffer amplifier, which prevents loading of the input signal, accepts at its input an amplified and equalized pseudo-ternary signal. The output of the buffer amplifier is a-c coupled to the input of a precision differential amplifier, from which two output signals are obtained. One said output signal is representative of the positive pulses and the other said output signal is representative of the negative pulses of the pseudo-ternary signal. These two output signals are both applied to the inputs of a peak detector and a slicer. The d-c output of the peak detector is also applied as one input to the slicer. Separate outputs are obtained from the slicer, one each for the positive and negative pulse inputs, and these two outputs are summed, and the summed output is then amplified to provide a clock driver output.

REFERENCES:
patent: 3657732 (1972-04-01), Krause
patent: 3707683 (1972-12-01), Dotter
patent: 3947697 (1976-03-01), Archer et al.
patent: 4027178 (1977-05-01), Larner
patent: 4064541 (1977-12-01), Schneider et al.

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