Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2009-01-16
2010-12-07
Stark, Jarrett J (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S691000, C257SE23151
Reexamination Certificate
active
07847408
ABSTRACT:
An integrated clock and power distribution network in a semiconductor device includes assigning a first tile to a location on a placement grid corresponding to a top metal layer. An orientation is assigned to the first tile relative to the top metal layer placement grid. The first tile is placed on a representation corresponding to the top metal layer in accordance with the assignments. A second tile is assigned to a location on a placement grid corresponding to a top-1 metal layer. The orientation is assigned to the second tile relative to the top-1 metal layer placement grid. The second tile is placed on a representation corresponding to the top-1 metal layer in accordance with the assignments. The first and second tile are arranged as a full-dense-mesh distribution structure. The first tile includes an integrated clock and power distribution structure. The second tile includes a low impedance underpass structure.
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International Search Report and the Written Opinion for PCT/US2009/044641 mailed Jan. 29, 2010 (16 pages).
Collier Duncan
Masleid Robert P.
Oracle America Inc.
Osha • Liang LLP
Stark Jarrett J
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