Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1996-05-31
2002-11-19
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S192000, C257S609000
Reexamination Certificate
active
06483134
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to mitigating or eliminating single event effects in integrated circuits that would otherwise be susceptible to single event effects. More particularly, the present invention relates to decreasing the free carrier lifetime of electrons and holes that would otherwise contribute to single event effects, through the use of a buffer layer.
2. Description of the Related Art
Three major types of radiation-induced effects are generally recognized as potential interferents with integrated circuits: total dose effects, transient effects, and soft errors (a.k.a. single event effects). Some other effects, e.g. neutron damage, are recognized by some practitioners.
Total dose effects are related to the permanent failure of an entire integrated circuit caused by an accumulation of radiation, e.g., x- or &ggr;-rays. Such exposure can cause permanent threshold voltage shifts in integrated circuits that are not hardened against total dose radiation. As the name suggests, total dose radiation effects are related to the entire exposure history of integrated circuits—when the total dose exceeds some threshold value, circuit failure is observed. GaAs technology is inherently less susceptible to total dose effects than other technologies.
Transient effects are likewise caused by the exposure of an entire integrated circuit to a flood of radiation, typically x- or &ggr;-rays. However, these are typically related to a short burst (10-20 ns) of high intensity radiation, such as that emitted by a nuclear detonation. Such exposure can cause temporary, and in some case permanent, failure in integrated circuits that are not hardened against transient effect radiation.
Single event effects are a distinct phenomenon from total dose and transient effects. See generally Sherra E. Kerns,
Transient
-
Ionization and Single
-
Event Phenomena,
in Ionizing Radiation Effects in MOS Devices and Circuits 485-91 (John Wiley & Sons, Inc., T. P. Ma et al. eds., 1989). Unlike total dose effects and transient effects, single event effects are localized to a particular region of an integrated circuit. Single event effects occur when a particle (such as a cosmic ray, proton, or neutron) changes the state of a particular device in an integrated circuit, thereby causing an error.
Single event effects that take place in memory chips are referred to as single event upsets. These occur when an element in a memory chip has its state changed (i.e., from a 1 to a 0 or from a 0 to a 1) by the action of a high energy particle interacting with the chip. In memory chips, the frequency of single event upsets will depend principally on the use environment and on the configuration of the memory chip. Single event effects also will occur in other logic chips, e.g., microprocessors. In these chips, the frequency of single event effects will depend on the clock speed of the device, as well as on the use environment and configuration of the device. This clock speed dependence arises from the fact that at higher clock speeds, the fraction of time that a particular logic gate spends in transition from one state to another increases. Edge-triggered devices are susceptible to soft errors in the transition region. Consequently, the larger fraction of time high-speed devices spend in the transition region increases the window of susceptibility to soft errors. The technological trend for the past several years has been toward edge-triggered circuits and away from comparative level-triggered circuits.
A number of factors can contribute to the frequency of single event effects in a device. The factor that has been most well documented to date is the use environment of the device. Electronic devices used in outer space, for instance, are bombarded with cosmic rays and protons that will induce soft errors in unhardened ICs. To date, the only effective methods for hardening these circuits against cosmic rays and protons have been shielding, redundancy, and error detection and correction (EDAC).
Likewise, neutrons, alpha particles, and other high energy particles will induce single event effects in devices that are used in environments that have high concentrations of these particles. It would be desirable, for example, to operate satellites within the Van Allen belts. However, this is currently impossible without the use of shielding, redundancy, and/or EDAC, due to the high particle concentrations within the Van Allen belts.
Even at elevations within the atmosphere, e.g. at elevations of 20,000 to 50,000 feet, single event effects can create electronic errors. It has been established that single event effects can interfere with airborne electronics.
Even at sea level, the concentration of single event-inducing particles is nonzero. To date, this has not been a major concern because single event effects are uncommon at sea level. This is due to the still relatively slow clock speeds and large device sizes in the digital electronics in use today. However, high-speed supercomputers and other cutting edge technologies may already be experiencing some errors that may be associated with single events. As typical clock speeds increase, past 250 MHz, to 500 MHz, 1 GHz, 2 GHz, and beyond, the occurrence of single event effects will increase proportionately. Aggravating this increase in clock speeds is the decreasing size of the transistors in ICs. A smaller device generally has a smaller capacitance, and accordingly will require a smaller charge to cause the device to change its state. Thus, it can be predicted that, for example, a GaAs IC (FET technology) with a clock speed of 1 GHz, with a device density of 10
6
transistors, will have an unacceptably high error rate, on the order of about 1-10 errors/day at sea level under normal conditions or about 10-1000 errors/day at sea level during solar events.
It is also desired to improve the isolation of devices in ICs, reducing leakage currents.
Calawa et al., U.S. Pat. No. 4,952,527, teaches the use of 2.0 &mgr;m buffer layers of low-temperature grown GaAs under III-V semiconductor microwave devices, to improve their back-gating effects and their resistivity, and also to improve their hardness against transient radiation.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide digital ICs that have improved resistance to single event effects, by several orders of magnitude.
It is a further object of this invention to provide such resistance without the need for additional shielding or redundancy.
It is a further object of this invention to provide such resistance in ICs that are of at least MSI, LSI, or VLSI complexity.
It is a further object of this invention to provide such resistance in ICs that have high clock speeds.
It is a further object of this invention to provide improved isolation of devices in ICs.
These and additional objects of the invention are accomplished by the structures and processes hereinafter described.
The present invention is an electronic device having a buffer layer characterized by short carrier lifetimes within the buffer layer, this buffer layer being at least about 1000 Å thick and having an upper face, and an integrated circuit disposed over the upper face of the buffer layer, where this integrated circuit would otherwise be susceptible to soft errors, due to its configuration, its clock speed, its use environment, or a combination of these factors. As used herein, “over”, “under”, “upper”, “lower” and the like are used as relative terms for convenience only, and do not require or imply any particular orientation with respect to gravitational fields.
REFERENCES:
patent: 4887236 (1989-12-01), Schloemann
patent: 4952527 (1990-08-01), Calawa et al.
patent: 4979003 (1990-12-01), Wennekers
patent: 5081062 (1992-01-01), Vasudev et al.
patent: 5332918 (1994-07-01), Smith et al.
patent: 5411914 (1995-05-01), Chen et al.
patent: 5594262 (1997-01-01), Lee et al.
Marshall Et Al “Heavy Ion SEU Immunity of a GAAs Complementary HIGFET Circuit Fabricated on a Low Temperature Gro
Curtice Walter R.
McMorrow Dale P.
Weatherford Todd R.
Karasek John J.
Legg Lawrence G.
Munson Gene M.
The United States of America as represented by the Secretary of
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