Integrated circuits with borderless vias

Details Integrated circuits with borderless vias Integrated circuits with borderless vias

1996-01-11

1998-05-26

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Beam leads

257751, 257752, 257753, 257758, H01L 2348, H01L 2352, H01L 2940

Patent

active

057570779

ABSTRACT:
A method of forming interconnecting layers in a semiconductor device whereby even if a via is misaligned with a metal line, a portion of the via not enclosed and capped by the metal is enclosed and capped by an etch stop spacer. The foundation layer includes a dielectric layer having a trench formed therein, the trench being filled with a plug material. The foundation layer further includes a barrier layer formed atop the dielectric layer. A metal layer is formed on the surface of the boundary layer, and a protection layer is formed on the surface of the metal layer. The protection layer and the metal layer are patterned to define a line of composite protection/metal on the surface of the boundary layer. An etch stop layer is formed which substantially conforms to the shape of the composite protection/metal line, including etch stop spacers conforming to the sidewall portions of the line. Selected portions of the etch stop layer are removed to expose the protection surface of the composite protection/metal line and portions of the boundary layer, while leaving the etch stop spacers. Portions of the boundary layer between the etch stop spacers are removed. A layer of via dielectric is formed that covers, and extends above, the line. A portion of the via dielectric layer above the composite protection/metal line is removed, exposing a portion of the protection surface of the composite protection/metal line. Finally, a portion of the protection surface from the composite protection/metal line is removed, leaving the metal portion of the line only.

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