Excavating
Patent
1994-04-04
1996-09-17
Beausoliel, Jr., Robert W.
Excavating
371 211, 371 212, G06F 1100, G06F 1127
Patent
active
055576192
ABSTRACT:
A processor-based Array Built-in Self Test (ABIST) circuit that generates self-test patterns for high speed SRAMs or DRAMs having a short access time. The circuit includes three main blocks: a conventional address generator for generating self-test addressing signals, a subset of which are used by a control logic main block. This control logic block forces proper signal sequencing of the processing main block during the ABIST mode. The processing main block includes, preferably, three generators for preparing signals for use during the next cycle. These signals are respectively stored in two latches to generate the corresponding expected output data one cycle later. The processor-based ABIST circuit allows for faster data generation, minimal semiconductor area consumption, extended programmability and full compatibility.
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"Dynamic Self-Repair Redundancy System" IBM Corp., Technical Disclosure Bulletin, V. 34, No. 5, pp. 448-449, Oct. 1991.
Beausoliel, Jr. Robert W.
International Business Machines - Corporation
Iqbal Nadeem
Schnurmann H. Daniel
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