Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-03-02
2001-03-27
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S513000
Reexamination Certificate
active
06208008
ABSTRACT:
TECHNICAL FIELD
The present invention is generally directed to the manufacture of integrated circuits and, in particular, to the prevention of cracking in the final passivation layer of an integrated circuit by reducing stress in the surrounding dielectrics.
BACKGROUND OF THE INVENTION
Current metal patterning methods, including reactive ion etching (RIE) and damascene techniques, use anisotropic etching processes that make it possible to produce patterns having features with dimensions on the order of sub-half micron in size. In practice, such anisotropic etching results in the development of sharp corners (i.e., when viewed through the cross-section of the metal layer).
For example,
FIGS. 1A and 1B
schematically illustrate integrated circuits
1
,
2
which have been produced using an RIE process (
FIG. 1A
) and a damascene process (FIG.
1
B), respectively. In each case, desired metallized features
3
(e.g., conductor lines formed of aluminum) are shown associated with a suitable substrate
4
(e.g., formed of SiO
2
). For the RIE-prepared integrated circuit
1
of
FIG. 1A
, an outer layer
5
(e.g., including Si
3
N
4
and SiO
2
) is applied over the features
3
and the substrate
4
. For the damascene-prepared integrated circuit
2
of
FIG. 1B
, the metallized features
3
are received within trenches
6
formed in the substrate
4
.
In practice, such processing results in sharp corners
7
′,
7
″ (seen through the cross-section of the metallized features
3
), respectively, along the tops
8
and at the bottoms
9
of the metallized features
3
. The sharp corners
7
′,
7
″ tend to cause high stresses in the surrounding dielectrics. These high stresses have been found to cause cracks in the final passivation layer. S. Lee & K. Lee, “The Optimization of Passivation Layout Structure for Reliability Improvement of Memory Devices,” Jpn. J. Appl. Phys., Vol. 35, Part 1, No. 10, pp. 5462-65 (Oct. 1996). These high stresses have also been found to cause “cratering” in the fuses which have come to be formed on integrated circuits for various purposes, when such fuses are laser-blown.
In an effort to reduce stress-induced cracking, Lee et al. suggest increasing the passivation thickness. The authors recognize, however, that the beneficial effects of this suggestion are limited by a corresponding increase in the brittleness of a thicker layer. U.S. Pat. Nos. 5,416,048; 4,425,183; and 4,352,724 each suggest rounding of the top corners
7
′ to achieve various improvements in the etching of semiconductors. For U.S. Pat. Nos. 5,416,048 and 4,425,183, and as is further disclosed in U.S. Pat. No. 4,780,429, the etched metallized features
3
can further be provided with sloping sides to achieve various other improvements. The sloping sides resulting from such manufacturing processes are formed, however, using the oxides of the metals which form the metallized features
3
. Such formation has been found to yield moderately high leakage currents and, at times, to extend across the gap which must be preserved between the adjacent metallized features
3
(e.g., adjacent metal vias or lines).
Therefore, the primary object of the present invention is to reduce deleterious effects, such as cracking of the final passivation layer or “cratering” of the fuse layer of a manufactured integrated circuit, by reducing the high stresses which can be developed in the dielectrics which surround the features being formed on the integrated circuit. Another object of the present invention is to accomplish this in a way which is fully compatible with conventional metal patterning methods, including RIE and damascene techniques.
SUMMARY OF THE INVENTION
These and other objects, which will become apparent, are achieved in accordance with the present invention by rounding bottom corners of the features formed as part of an integrated circuit, such as the “interconnects” of the integrated circuit, before applying the outer (i.e., passivation) layer.
In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall. This process results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. Such corner rounding can also be achieved by producing a tapered insulating sidewall along the feature (i.e., the metal line or via) by applying a flowable glass (such as a spin-on-glass) layer to lower portions of the feature, followed by etching of the applied glass layer to form a spacer. This process results in a bottom corner having a sidewall formed from the flowable glass which is tapered, rather than vertical, again improving the step coverage of the overlying dielectric.
For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
REFERENCES:
patent: 4352724 (1982-10-01), Sugishima et al.
patent: 4425183 (1984-01-01), Maheras et al.
patent: 4462882 (1984-07-01), Horwitz
patent: 4729815 (1988-03-01), Leung
patent: 4780429 (1988-10-01), Roche et al.
patent: 4981551 (1991-01-01), Palmour
patent: 4981810 (1991-01-01), Fazan et al.
patent: 5106770 (1992-04-01), Bulat et al.
patent: 5317193 (1994-05-01), Watanabe
patent: 5416048 (1995-05-01), Blalock et al.
patent: 5489548 (1996-02-01), Nishioka et al.
patent: 5514624 (1996-05-01), Morozumi
patent: 5830797 (1998-11-01), Cleeves
patent: 5-90258 (1993-04-01), None
patent: 9-232305 (1997-09-01), None
patent: WO 98/42020 (1998-09-01), None
EPO Search Report Dated Jul. 27, 1999.
S. Lee & K. Lee, The Optimization of Passivation Layout Structure for Reliability Improvement of Memory Devices, Jpn. J. Appl. Phys., vol. 35, Part 1, No. 10, pp. 5462-5465 (Oct. 1996).
Arndt Kenneth C.
Conti Richard A.
Dobuzinsky David M.
Economikos Laertis
Gambino Jeffrey P.
Capella, Esq. Steven
Hardy David
International Business Machines - Corporation
Ratner & Prestia
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