1985-12-11
1988-08-16
Eisenzopf, Reinhard J.
Excavating
371 27, G01R 3128
Patent
active
047649267
ABSTRACT:
An integrated circuit having a built-in self test facility, the integrated circuit being partitioned into a number of sub-circuits each of which comprises a combinatorial logic circuit and a register. The sub-circuits are coupled together so that each combinatorial logic circuit has its inputs coupled to at least one register, has its outputs coupled to at least one register, and the output of the overall integrated circuit is taken from one or more registers. Each register has its fucntional mode controlled by predetermined signals to an associated local decoder, the functional modes of the registers being selected to initiate a test operation for the testing of the integrated circuit.
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Burrows David F.
Knight William L.
Paraskeva Mark
Burns W.
Eisenzopf Reinhard J.
Oglo Michael F.
Plessey Overseas Limited
Renfro Julian C.
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