Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Patent
1994-04-28
1996-02-20
Hajec, Ddonald T.
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
257 67, 257401, 257900, H01L 2976
Patent
active
054931304
ABSTRACT:
The disclosure pertains to a bottom and top gated thin film transistor and other circuitry constructions. In the thin film transistor construction, the top gate electrode (preferably polysilicon) overlaps with the channel region, and the top gate electrode has an electrically conductive sidewall (preferably oxide). The bottom gate electrode (preferably polysilicon) has an outer surface area which includes a portion which extends outwardly beyond the top gate electrode sidewall. An electrically conductive sidewall link overlies the electrically insulated channel region sidewall and extends between the top gate sidewall and bottom gate outer surface portion to electrically interconnect the top and bottom gate electrodes. The insulated channel region sidewall is insulated by an insulating sidewall spacer. The insulating sidewall spacer partially overlaps the top gate electrode electrically conductive sidewall. More generally beyond thin film transistor constructions, two conductive layers are provided which are separated by an insulating material on a semiconductor wafer. Each has an outer sidewall. An electrically conductive sidewall link is positioned over and electrically interconnects the respective outer sidewalls of the two conductive layers. Further, a mid conductive layer is provided which is electrically isolated from and positioned between the inner and outer conductive layers. This layer has a sidewall also covered by an insulating material. The insulating material partially overlaps the outer conductive layer sidewall. The electrically conductive sidewall link is positioned over the insulating material.
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patent: 5338959 (1994-08-01), Kim et al.
Colinge, J. P. et al.; "Silicon-On-Insulator `Gate-All-Around Device`", IEEE, IEDM 90-595-599 (1990).
Tanaka, T. et al.; "Analysis of P.sup.30 PolySi Double-Gate Thin-Film SOI MOSFETS", IEEE, IEDM 91-683-686, (1981).
Dennison Charles H.
Manning Monte
Hajec Ddonald T.
Micro)n Technology, Inc.
Tremblay Mark
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