Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Patent
1998-01-29
1999-11-02
Carroll, J.
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
438601, 438625, 257529, 257665, H01L 2900
Patent
active
059769173
ABSTRACT:
Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided. The programming circuitry comprises at least one MOS device which is capable of being utilized to provide a programming voltage which is sufficient to blow the fuse, and which is no greater than the breakdown voltage of the one MOS device.
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Carroll J.
Micro)n Technology, Inc.
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