Static information storage and retrieval – Floating gate – Particular connection
Patent
1996-02-16
1998-01-13
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular connection
365200, 365201, G11C 700
Patent
active
057086010
ABSTRACT:
An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default state until it is programmed with an address of one of the defective memory cells. A control circuit generates a test signal during an identification mode. A detect circuit is coupled to the control circuit and to the redundancy address register and generates a default-detect signal in response to the test signal when the redundancy address register contains the default state. A data-bus multiplexer that is coupled to the redundancy-cell selection circuit, the data bus, and the control circuit couples the default detect signal to the data bus in response to the test signal.
REFERENCES:
patent: 4586170 (1986-04-01), O'Toole et al.
patent: 5124949 (1992-06-01), Morigami
patent: 5493531 (1996-02-01), Pascucci et al.
Maccarrone Marco
McKenny Vernon G.
Pascucci Luigi
Carlson David V.
Popek Joseph A.
Santarelli Bryan A.
SGS--Thomson Microelectronics S.r.l.
LandOfFree
Integrated circuitry for checking the utilization rate of redund does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuitry for checking the utilization rate of redund, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuitry for checking the utilization rate of redund will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-331567