Integrated circuit with unequally-sized, paired memory coupled t

Details Integrated circuit with unequally-sized, paired memory coupled t Integrated circuit with unequally-sized, paired memory coupled t

1995-06-07

1997-04-29

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Plural blocks or banks

365 51, 365 63, 36518902, 36523002, 36523004, G11C 700

Patent

active

056256035

ABSTRACT:
An integrated circuit with an integer odd number C of electrical contacts, wherein each of the electrical contacts is for communicating a data value. The integrated circuit also includes four memory arrays for storing data. The first and third memory arrays are operable to simultaneously output an integer even number E of data values. The second and fourth memory arrays are operable to simultaneously output an integer odd number D of data values. The integrated circuit further includes circuitry for selectively coupling the first, second, third, and fourth memory arrays to the electrical contacts, wherein the circuitry for selectively coupling is operable to couple the first and fourth memory arrays to the electrical contacts in a first state so that the first memory array outputs E data values and the fourth memory array outputs D data values in the first state. The circuitry for selectively coupling is also operable to couple the second and third memory arrays to the electrical contacts in a second state so that the second memory array outputs D data values and the third memory array outputs E data values in the second state.

REFERENCES:
patent: 5121354 (1992-06-01), Mandalia
patent: 5416749 (1995-05-01), Lai
patent: 5493535 (1996-02-01), Cho
patent: 5499216 (1996-03-01), Yamamoto

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