Integrated circuit with tungsten plug containing amorphization l

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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257752, 257753, 257758, H01L 2348

Patent

active

060160098

ABSTRACT:
A process of forming a tungsten contact plug, on an integrated circuit (IC), that is substantially free of seam formation is described. The process includes forming a dielectric layer on a surface of a substrate, forming a via in the dielectric layer, blanket depositing a first bulk layer of tungsten on the dielectric layer and partially filling the via, blanket depositing an amorphous or a microcrystalline layer of tungsten over the first bulk layer of tungsten such that growth of tungsten grains inside the via is effectively inhibited, and blanket depositing a second bulk layer of tungsten on the amorphous or microcrystalline layer.

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Author Unknown, "Process Characterization", User's Guide to Tungsten Processing, p. 5-2 (prior to Mar. 20, 1998).
M. Iwasaki, et al., Blanket CVD-W Formed by H.sub.2 Reduction of WF.sub.6 on Tin for Planar Interconnection, Materials Research Society, Symposium Proc. VLSI V, (1990).
John E.J. Schmitz. "Chemical Vapor Deposition of Tungsten and Tungsten Silicides for VLSI/ULSI Applications", Noyes Publications, USA, 1992, pp. 32, 33, 64-67, 102-103.
M. Iwasaki, H. Itoh, T. Katayama, K. Tsukamoto and Y. Akasaka, "Blanket CVD-W Formed by H.sub.2 Reduction of WF.sub.6 on Tin for Planar Interconnection" Mat.Res.Soc. Synp.Proc. VLSI V, 1990, pp. 187-193.
R.V. Joshi, E. Mehter, M. Chow, M. Ishaq, S. Kang, P. Geraghty and J. Mclnerney, "High Growth Rate CVD--W Process For Filling High Aspect Ratio Sub-Micron Contacts/Lines" Mat.Res.Soc.Symp.Proc.VLSI V, 1990, pp. 157-166.
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