Integrated circuit with stress isolated Hall element

Details Integrated circuit with stress isolated Hall element Integrated circuit with stress isolated Hall element

1984-04-16

1986-03-25

Edlow, Martin H.

357 48, H01L 2722, H01L 2704

Patent

active

045786925

ABSTRACT:
A silicon integrated circuit includes a centrally located Hall element having an annular moat region surrounding the Hall element to isolate it from built in stresses in adjacent parts of the integrated circuit. The moat comprises at least one annular isolation wall, but preferably two concentric isolation walls. This moat construction also leads to a reduction in dependency of Hall element symmetry upon process variables.

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IBM Journal, 1966, Kennedy et al., "Calculations of Impurity Atom Diffusion . . . ", pp. 6-12.
Physical Review, vol. 94, No. 1, Apr. 1, 1954, Smith, C. S., "Piezoresistance Effects in Ge. and Si.", pp. 42-49.
Ravi, Imperfections and Impurities in Semiconductor Silicon, J. Wiley & Sons, N.Y., 1981.

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