Integrated circuit with silicon contact to silicide

Details Integrated circuit with silicon contact to silicide Integrated circuit with silicon contact to silicide

1991-12-30

1997-01-07

Quach, T. N.

Fishing, trapping, and vermin destroying

437200, 437 20, 748DIG147, H01L 21265, H01L 21283

Patent

active

055916740

ABSTRACT:
An integrated circuit is described which has an electrical contact formed between a metallic silicide and .alpha.:Si. The method of integrated circuit manufacturing comprising the steps of: forming a layer of a metallic silicide; depositing a layer of .alpha.:Si on said metallic silicide at a temperature less than the recrystallization temperature; and increasing the conductivity of at least selected portions of said .alpha.:Si by ion implanting a species having the peak of its spatial distribution spaced from the .alpha.:Si-Silicide interface and the .alpha.:Si surface.

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patent: 4569121 (1986-02-01), Lim et al.
patent: 4569122 (1986-02-01), Chan
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patent: 4727045 (1988-02-01), Cheung et al.
patent: 5010037 (1991-04-01), Lin et al.
patent: 5025741 (1991-06-01), Suwanai et al.
"A Large Cell-Ratio and Low Node Leak 16M-bit SRAM Cell", by K. Yuzuriha et al., pp. 485-488., IEDM Tech. Dig., Dec. 1991.
"Low Threshold Stacked CMOS Devices Utilizing Self-Aligned Silicide Technology", IBM Tech. Disc. Bull., vol. 28, No. 4, Sep. 1985, pp. 1431-1432.
Wolf, S., et al., Silicon Processing for the VLSI Era, vol. 1, Process Technol., Lattice Press, 1986, pp. 283-308, 384-387.

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