Integrated circuit with shielded lead patterns

Details Integrated circuit with shielded lead patterns Integrated circuit with shielded lead patterns

1979-05-31

1982-02-02

Larkins, William D.

357 50, 357 53, 357 84, H01L 2704

Patent

active

043142680

ABSTRACT:
A semiconductor integrated circuit device is designed to prevent capacitive coupling between a wiring layer and respective circuit elements in the integrated circuit device. A plurality of island regions are provided along one major surface of a semiconductor substrate, and an insulating film is formed on the one major surface of the substrate. A first wiring layer on the insulating film is connected at a first contact section to an impurity region of one conductivity type within one island region among the plurality of island regions. A second wiring layer on the insulating film is connected at a second contact section to a first impurity region of opposite conductivity type within the one island region. A third wiring layer on the insulating film is connected to another island region among the plurality of island regions and extends over the portion of the one island region between the first contact section and the first impurity region of opposite conductivity type. A second impurity region of the opposite conductivity type is provided along the one major surface in the portion of the one island region under the third wiring layer and separated from the first impurity region of the opposite conductivity type.

REFERENCES:
patent: 3373323 (1968-03-01), Wolfrum et al.
patent: 3573571 (1971-04-01), Brown et al.
patent: 3582727 (1971-06-01), Granger et al.
patent: 3631311 (1971-12-01), Engbert
patent: 3700977 (1972-10-01), Lunn

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