Integrated circuit with reduced clock skew

Details Integrated circuit with reduced clock skew Integrated circuit with reduced clock skew

1991-12-20

1994-01-11

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3074651, 3073031, H03K 1900, H01L 2500

Patent

active

052784665

ABSTRACT:
Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

REFERENCES:
patent: 4761567 (1988-08-01), Walters, Jr. et al.
patent: 4926066 (1990-05-01), Maini et al.
patent: 4958092 (1990-09-01), Tanaka
patent: 5045725 (1991-09-01), Sasaki et al.
patent: 5055710 (1991-10-01), Tanaka et al.
Nikkei Electronics, Sep. 5, 1988, "The Tron Specified Microprocessor Tx1 . . . ", Masuda et al., pp. 191-198.

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