Integrated circuit with protective moat

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Outside periphery of package having specified shape or...

Reexamination Certificate

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C257S773000, C257S758000, C257S784000, C257S786000, C257S700000, C257S774000, C257S734000, C257S748000, C257S750000, C438S424000, C438S462000

Reexamination Certificate

active

10768796

ABSTRACT:
A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.

REFERENCES:
patent: 5689134 (1997-11-01), Pasch et al.
patent: 6518673 (2003-02-01), Herr et al.
patent: 2002/0145196 (2002-10-01), Wang
patent: 2002/0167071 (2002-11-01), Wang
patent: 2003/0073257 (2003-04-01), Watanabe
patent: 2003/0134457 (2003-07-01), Kim et al.
patent: 2003/0160261 (2003-08-01), Moriya
patent: 2004/0084775 (2004-05-01), Sugino et al.
patent: 2004/0124546 (2004-07-01), Saran et al.

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