Integrated circuit with multiple independent gate field...

Details Integrated circuit with multiple independent gate field... Integrated circuit with multiple independent gate field...

2007-11-27

2007-11-27

Sherry, Michael (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

11130873

ABSTRACT:
A rail clamp circuit (100) includes first and second power supply voltage rails, a multiple independent gate field effect transistor (MIGFET) (128), and an ESD event detector circuit (138). The MIGFET (128) has a source/drain path coupled between the first (112) and second (114) power supply voltage rails, and first and second gates. The ESD event detector circuit (138) is coupled between the first (112) and second (114) power supply voltage rails, and has first and second output terminals respectively coupled to the first and second gates of the MIGFET. In response to an electrostatic discharge (ESD) event between the first (112) and second (114) power supply voltage rails, the ESD event detector circuit (138) provides a voltage to the second gate to lower an absolute threshold voltage of the MIGFET (128) while providing a voltage to the first gate above the absolute threshold voltage so lowered, thereby making the MIGFET (128) conductive with relatively high conductivity.

REFERENCES:
patent: 4385337 (1983-05-01), Asano et al.
patent: 5034845 (1991-07-01), Murakami
patent: 5237395 (1993-08-01), Lee
patent: 5239440 (1993-08-01), Merrill
patent: 5255146 (1993-10-01), Miller
patent: 5287241 (1994-02-01), Puar
patent: 5311391 (1994-05-01), Dungan et al.
patent: 5361185 (1994-11-01), Yu
patent: 5440162 (1995-08-01), Worley et al.
patent: 5515232 (1996-05-01), Fukazawa et al.
patent: 5559659 (1996-09-01), Strauss
patent: 5610790 (1997-03-01), Staab et al.
patent: 5654862 (1997-08-01), Worley et al.
patent: 5946177 (1999-08-01), Miller et al.
patent: 6385021 (2002-05-01), Takeda et al.
patent: 6714061 (2004-03-01), Hareland
patent: 6724603 (2004-04-01), Miller et al.
patent: 7075132 (2006-07-01), Lin et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: 2004/0219722 (2004-11-01), Pham et al.
patent: 2004/0235300 (2004-11-01), Mathew et al.
W.D. Mack and R.G. Meyer, “New ESD Protection Schemes for BiCMOS Processes with Application to Cellular Radio Designs,” ISCAS Proceedings 1992.
E. R. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen, and M. Tennyson, “Sub-micron Chip ESD Protection Schemes which Avoid Avalanching Junctions,” Proc. EOS/ESD Symposium, pp. 13-20, 1995.
G. Croft, “Transient Supply Clamp with a Variable RC Time Constant,” EOS/ESD Symp. Proceedings, 1996, pp. 276-279.
W. Anderson, J. Montanaro and N Howorth, “Cross-Referenced ESD Protection for Power Supplies,” EOS/ESD Symp. Proceedings, 1998.
J.C. Bernier, G.D. Croft, and W.R. Young, “A Process Independent ESD Design Methodology,” ISCAS Proceedings, 1999.
Richard Merrill and Enayet Issaq, “ESD Design Methodology,” National Semiconductor Fairchild Research Center, EOS/ESD Symposium, 1993.
Cynthia A. Torres et al. “Modular, Portable, and Easily Simulated ESD Protection Networks for Advanced CMOS Technologies,,” Motorola, Inc.
Michael Stockinger et al. “Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies,” EOS/ESD Symposium, Motorola, Inc., 1993.
Patrick A. Juliano and Warren R. Anderson ESD Protection Design Challenges for a High Pin-Count Alpha Microprocessor in a 0.13 um CMOS SOI Technology, EOS/ESD Symposium, Motorola, Inc., 1993.
Gen Pei and Edwin Chih-Chuan Kan, “Independently Driven DG MOSFETs for Mixed-Signal Circuits: Part I—Quasi-Static and Nonquasi-Static Channel Coupling,” IEEE Transactions, vol. 51, No. 12, Dec. 2004.
Gen Pei and Edwin Chih-Chuan Kan, “Independently Driven DG MOSFETs for Mixed-Signal Circuits: Part II—Applications on Cross-Coupled Feedback and Harmonics Generation,” IEEE Transactions, vol. 51, No. 12, Dec. 2004.

Affiliated with

Also associated with

Rating

Integrated circuit with multiple independent gate field... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit with multiple independent gate field..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit with multiple independent gate field... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3884902