Integrated circuit with mode control for selecting settled...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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11057450

ABSTRACT:
In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

REFERENCES:
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patent: 6141671 (2000-10-01), Adams et al.
patent: 6321246 (2001-11-01), Page et al.
Matlab, Signal Processing Toolbox for Use with matlab: Chapter 5 Interactive Tools, 1998, the Math Works Inc., Ver. 4, pp. 5-1 to 5-33.
Hurst et al., Finite Impulse Response Switched-Capacitor Filters for the Delta-Sigma Modulator D/A Interface, IEEE transactions on circuits and systems, vol. 38, No. 11, Nov. 1991, pp. 1391-1397.
Johnston, A 24-bit delta-sigma ADC with an ultra-low noise chopper-stabilitized programmable gain instrumentation amplifer, IEEE, Conference Publication No. 466, Jul. 1999, pp. 179-182.

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