Integrated circuit with memory self-test

Details Integrated circuit with memory self-test Integrated circuit with memory self-test

1986-10-02

1989-10-03

Atkinson, Charles E.

Excavating

371 224, G01R 3128

Patent

active

048721689

ABSTRACT:
A memory array included with logic circuitry on an integrated circuit is tested by a technique that reads and writes a specified sequence of test bits into a given memory word before progressing to the next word. A checkerboard pattern of 1's and 0's is written into the physical memory locations. This provides for an improved worst-case test while allowing case of implementation for the test circuitry. The test results from a comparator circuit may be compressed to provide one (or a few) test flags indicating whether the memory passed the test, requiring a minimal number of test pads or terminals for the chip.

REFERENCES:
patent: 3751649 (1973-08-01), Hart, Jr.
patent: 3863227 (1975-01-01), Sanabria
patent: 4061908 (1977-12-01), de Jonge et al.
patent: 4342084 (1982-07-01), Sager et al.
patent: 4369511 (1983-01-01), Kimura et al.
patent: 4429389 (1984-01-01), Catiller
patent: 4441074 (1984-04-01), Bockett-Pugh et al.
patent: 4488300 (1984-12-01), Horey et al.
patent: 4502131 (1985-02-01), Giebel
patent: 4503536 (1985-03-01), Panzer
patent: 4594711 (1986-06-01), Thatte
1981 IEEE Test Conference, "Paragons for Memory Test", Paper 3.3, pp. 44-48, by S. Winegarden and D. Pannell, Amdahl Corp.
1985 International Test Conference, "Self-Test of Random Access Memories", Paper 10.1, pp. 352-355, by P. Bardell & W. McAnney.
1984 International Test Conference, "Self-Testing of Embedded RAMS", Paper 4.3, pp. 148-156, by Z. Sun and L. Wang.
1981 IEEE Test Conference, "The Self-Assist Test Approach to Embedded Arrays", Paper 9.1, pp. 203-207, by D. Westcott, IBM.
IEEE Transactions on Computers, vol. C-27, No. 6, Jun. 1978, "Efficient Algorithms for Testing Semiconductor Random-Access Memories", pp. 572-576, by R. Nair, S. Thatte, & J. Abraham.
IEEE Transactions on Computers, vol. C-28, No. 6, Mar. 1979, "Comments on an Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories", pp. 258-261, by Ravindra Nair, IBM, Thomas J. Watson Research Center.
IEEE Transactions on Computers, vol. C-26, No. 11, Nov. 1977, "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories", pp. 1141-1144, by J. Knaizuk, Jr. and Carlos R. P. Hartmann.
IEEE Design and Test, "Built-In Self-Test Techniques", Apr. 1985, pp. 21-28, by E. McCluskey, Stanford University.
IEEE Transactions on Computers, vol. C-29, No. 6, Jun. 1980, "Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories", pp. 419-429, by Dong S. Suk and Sudhakar M. Reddy.

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