Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-05-12
2001-09-25
Wong, Don (Department: 2821)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C438S221000, C438S634000
Reexamination Certificate
active
06294823
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and a method for making them.
BACKGROUND OF THE INVENTION
To continue adding transistors to integrated circuits without significantly increasing die sizes, the distance between transistors and other devices may have to be reduced. The need to reduce the distance between devices may require reducing the width of the landing area for the contacts. As a result, when contact is made to the landing area, part of the contact may extend laterally over the isolation structure, forming a borderless contact. To prevent the contact etch step from etching into the isolation structure, an etch stop layer may be formed on the surface of the device prior to performing the contact etch. Such a layer may comprise silicon nitride.
Processes that add such an etch stop layer require extra steps, e.g., an extra nitride layer deposition step and a two step contact etch. Moreover, where such a nitride etch stop layer is formed over a silicide, the nitride must be deposited at a relatively low temperature to maintain junction and silicide integrity. Depositing nitride using a low temperature process may, however, adversely affect a device's reliability. In addition, when a relatively thick nitride layer is used to form the etch stop, e.g., to ensure the contact etch will not completely remove that layer, that layer may require devices to be spaced further apart. Requiring additional spacing to accommodate a thick nitride layer may diminish the reduced spacing benefit that borderless contacts may otherwise provide.
Accordingly, there is a need for a method for making borderless contacts that either eliminates altogether the need to form a silicon nitride etch stop layer after silicide formation, or allows for the use of a thinner nitride etch stop layer.
SUMMARY OF THE INVENTION
The present invention covers an integrated circuit comprising a shallow trench isolation structure formed adjacent to a well, a borderless contact making electrical contact to a conductive region formed on the well, and an insulating spacer formed adjacent to a sidewall of the conductive region. The present invention also covers a method of forming such an integrated circuit.
REFERENCES:
patent: 4966870 (1990-10-01), Barber et al.
patent: 5268330 (1993-12-01), Givens et al.
patent: 5348905 (1994-09-01), Kenney
patent: 5466636 (1995-11-01), Cronin et al.
patent: 5633202 (1997-05-01), Brigham et al.
patent: 5652176 (1997-07-01), Maniar et al.
patent: 5926693 (1999-07-01), Gardner et al.
patent: 5972758 (1999-10-01), Liang
patent: 6090671 (2000-07-01), Balasubramanyam et al.
patent: 6093619 (2000-07-01), Huang et al.
patent: 6096642 (2000-08-01), Wu
Arafa Mohamed
Thompson Scott
Alemu Ephrem
Intel Corporation
Seeley Mark
Wong Don
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