Integrated circuit with improved pre-metal planarization

Details Integrated circuit with improved pre-metal planarization Integrated circuit with improved pre-metal planarization

1997-08-20

1999-05-11

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257760, 257774, 257915, H01L23/48

Patent

active

059030542

ABSTRACT:
An integrated circuit wherein a planarization step has been performed before the primary metal deposition step, but after deposition of the adhesion and barrier layers. Thus the adhesion and barrier layers are present on the sidewalls of contact holes, but do not underlie the whole extent of the primary metallization.

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patent: 5233217 (1993-08-01), Dixit et al.
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patent: 5486492 (1996-01-01), Yamamoto et al.
Translation of Japan Kokai Publication #01-0140768 (Jun. 1989) to Shinohara, 10 pages.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2 Lattice Press, 1990, p. 128.

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