Integrated circuit with improved power supply distribution

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365 63, 365226, 36523003, G11C 514

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active

050401440

ABSTRACT:
An integrated circuit with reduced size through improved power supply distribution. A bonding pad supplies V.sub.SS to an integrated circuit memory, which is distributed through a plurality of power supply lines in a first metal layer and a plurality of grid lines in a second metal layer intersecting at right angles. The plurality of grid lines are placed in unused spaced in the second metal layer and are coupled to the power supply lines in the first metal layer. Together the grid lines and the power supply lines provide an improved power supply by lowering the impedance from a point on the integrated circuit to V.sub.SS supplied on the bonding pad. While this technique is ideally suited to memory devices because of the repetitive nature of blocks of memory cells, other types of integrated circuits can also utilize such a power supply distribution technique.

REFERENCES:
patent: 4458297 (1984-07-01), Stopper et al.
patent: 4780846 (1988-10-01), Tanabe et al.
patent: 4849943 (1989-07-01), Pennings
"Power Grid Image for Embedded Arrays", IBM Technical Disclosure Bulletin, vol. 32, No. 813 Jan. 1990 pp. 451-452.

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