Integrated circuit with I.sup.2 L and power transistors and meth

Details Integrated circuit with I.sup.2 L and power transistors and meth Integrated circuit with I.sup.2 L and power transistors and meth

1979-03-12

1981-06-09

Larkins, William D.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148175, 148190, 148191, 357 48, 357 63, 357 90, 357 92, H01L 2174, H01L 2122, H01L 29167, H03K 19091

Patent

active

042723078

ABSTRACT:
An integrated circuit has a P-type substrate and two N-type epitaxial layers. P-type isolation walls define pockets in the dual-layer epitaxial material, a power transistor being formed in one and an inverted I.sup.2 L transistor being formed in another of the pockets. An upper buried layer doped with antimony (N-type) at the interface between the two epitaxial layers extends into the outer epitaxial layer forming a N.sup.+ N holes-barrier junction. This junction is spaced from the depletion region of the normally forward biased base emitter junction by from 0.1 to 0.45 holes-diffusion lengths to provide high emitter efficiency in 0.5 to 5 ohm-cm epitaxial material. The P-type bases of the two kinds of transistors have the same depth but the N-type emitter of the power transistor is shallower than the N-type collector of the inverted transistor although formed earlier. Breakdown voltage of the power transistor is thus enhanced while the base width of the I.sup.2 L transistor is predictable and uniform being substantially determined by late and independent process steps.

REFERENCES:
patent: 3707410 (1972-12-01), Tauchi et al.
Okabe et al., IEEE International Solid State Circuits Conf., Dig. Tech. Papers, Feb. 1978, pp. 44-45.
Watanabe et al., Proc. 8th Conf. on Solid-State Devices, Tokyo, 1976, pp. 143-146, (Japan J. of Applied Physics, Suppl. 16-1, 1977).
Bergmann, IEEE J. of Solid State Circuits, vol. SC 12, No. 5, Oct. 1977, pp. 566-572.
Yagi, Proc. 6th Conf. on Solid State Dev., Tokyo, 1974, pp. 279-283.

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