Patent
1989-12-01
1991-05-21
Larkins, William D.
357 36, 357 92, H01L 27082
Patent
active
050179977
ABSTRACT:
The invention relates to an integrated circuit having a transistor suitable for integrated injection logic (I.sup.2 L) with a single collector output region and having at least one base contact disposed between the collector output region (C.sub.60, C'.sub.60) and the injector (IN.sub.6), the surface of the collector output region being several times larger than that of a logic gate of the I.sup.2 L multi-collector type. The base (B.sub.60) has at least two rows of interconnected contacts: a first row (CB.sub.60, CB.sub.61, CB.sub.62) constituting the base contact disposed between the collector and the injector, and at least a second row (CB.sub.63, CB.sub.64, CB.sub.65) situated at the perimeter of the collector (C.sub.60,C'.sub.60), which can consist of one or several parts. The injector (IN.sub.6) may also have a row of interconnected contacts (CIN.sub.1, CIN.sub.2, CIN.sub.3).
REFERENCES:
patent: 3665266 (1972-05-01), Drozdowicz et al.
patent: 4163244 (1979-07-01), Ragonese et al.
Hart et al. Electronics, Oct. 3, 1974, pp. 111-118.
Berger, IEEE J of Solid State Circuits, vol. SC9, No. 5, Oct. 1974, pp. 218-227.
Korns, IEEE B of Solid State Circuits, vol. SC11, No. 5, Oct. 1976, pp. 712-717.
Chapron Claude E. P.
Parpaleix Jean B.
Biren Steven R.
Larkins William D.
U.S. Philips Corp.
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